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#ifndef _AC780X_CKGEN_H
#define _AC780X_CKGEN_H
/*!
 * @file ac780x_ckgen.h
 *
 * @brief This file provides clock generator module integration functions interfaces.
 *
 */
#ifdef __cplusplus
extern "C" {
#endif

/* ===========================================  Includes  =========================================== */
#include "ac7802x.h"

/* ============================================  Define  ============================================ */

/* ===========================================  Typedef  ============================================ */
/*!
 * @brief Clock module index enumeration.
 */
typedef enum
{
    /* PERI_CLK_EN_0 */
    CLK_UART0 = 0,
    CLK_UART1,
    CLK_RESERVE2,
    CLK_RESERVE3,
    CLK_RESERVE4,
    CLK_RESERVE5,
    CLK_SPI0,
    CLK_RESERVE7,
    CLK_I2C0,
    CLK_RESERVE9,
    CLK_PWDT0,
    CLK_PWM0,
    CLK_PWM1,
    CLK_PWM2,
    CLK_RESERVE14,
    CLK_RESERVE15,
    CLK_RESERVE16,
    CLK_RESERVE17,
    CLK_RESERVE18,
    CLK_TIMER,
    CLK_RTC,
    CLK_RESERVE21,
    CLK_RESERVE22,
    CLK_GPIO,
    CLK_RESERVE24,
    CLK_WDG,
    CLK_RESERVE26,
    CLK_RESERVE27,
    CLK_RESERVE28,
    CLK_RESERVE29,
    CLK_RESERVE30,
    CLK_RESERVE31,

    /* PERI_CLK_EN_1 */
    CLK_RESERVE32 = 32 + 0,
    CLK_CTU,
    CLK_ADC0,
    CLK_ACMP0,
    CLK_RESERVE36,
    CLK_RESERVE37,
    CLK_MODULE_NUM
} CKGEN_ClockType;

#define IS_CKGEN_CLOCK_PARA(CLOCK) (((CLOCK) == CLK_UART0) || \
                                    ((CLOCK) == CLK_UART1) || \
                                    ((CLOCK) == CLK_SPI0)  || \
                                    ((CLOCK) == CLK_I2C0)  || \
                                    ((CLOCK) == CLK_PWDT0) || \
                                    ((CLOCK) == CLK_PWM0)  || \
                                    ((CLOCK) == CLK_PWM1)  || \
                                    ((CLOCK) == CLK_PWM2)  || \
                                    ((CLOCK) == CLK_TIMER) || \
                                    ((CLOCK) == CLK_RTC)   || \
                                    ((CLOCK) == CLK_GPIO)  || \
                                    ((CLOCK) == CLK_WDG)   || \
                                    ((CLOCK) == CLK_CTU)   || \
                                    ((CLOCK) == CLK_ADC0)  || \
                                    ((CLOCK) == CLK_ACMP0))

/*!
 * @brief Soft reset module index enumeration.
 */
typedef enum
{
    /* PERI_SFT_RST1 */
    SRST_UART0 = 0,
    SRST_UART1,
    SRST_RESERVE2,
    SRST_RESERVE3,
    SRST_RESERVE4,
    SRST_RESERVE5,
    SRST_SPI0,
    SRST_RESERVE7,
    SRST_I2C0,
    SRST_RESERVE9,
    SRST_PWDT0,
    SRST_PWM0,
    SRST_PWM1,
    SRST_PWM2,
    SRST_RESERVE14,
    SRST_RESERVE15,
    SRST_RESERVE16,
    SRST_RESERVE17,
    SRST_RESERVE18,
    SRST_TIMER,
    SRST_RTC,
    SRST_RESERVE21,
    SRST_RESERVE22,
    SRST_GPIO,
    SRST_RESERVE24,
    SRST_WDG,
    SRST_RESERVE26,
    SRST_RESERVE27,
    SRST_RESERVE28,
    SRST_RESERVE29,
    SRST_RESERVE30,
    SRST_RESERVE31,

    /* PERI_SFT_RST2 */
    SRST_RESERVE32 = 32 + 0,
    SRST_CTU,
    SRST_ADC0,
    SRST_ACMP0,
    SRST_ANA_REG,
    SRST_RESERVE37,
    SRST_MODULE_NUM
} CKGEN_SoftResetType;

#define IS_CKGEN_SOFT_RESET_PARA(RESET) (((RESET) == SRST_UART0) || \
                                         ((RESET) == SRST_UART1) || \
                                         ((RESET) == SRST_SPI0)  || \
                                         ((RESET) == SRST_I2C0)  || \
                                         ((RESET) == SRST_PWDT0) || \
                                         ((RESET) == SRST_PWM0)  || \
                                         ((RESET) == SRST_PWM1)  || \
                                         ((RESET) == SRST_PWM2)  || \
                                         ((RESET) == SRST_TIMER) || \
                                         ((RESET) == SRST_RTC)   || \
                                         ((RESET) == SRST_GPIO)  || \
                                         ((RESET) == SRST_WDG)   || \
                                         ((RESET) == SRST_CTU)   || \
                                         ((RESET) == SRST_ADC0)  || \
                                         ((RESET) == SRST_ACMP0) || \
                                         ((RESET) == SRST_ANA_REG))

/*!
 * @brief System clock source enumeration.
 */
typedef enum
{
    SYSCLK_SRC_INTERNAL_OSC = 0,
    SYSCLK_SRC_EXTERNAL_OSC = 2
} SYSTEM_ClockSourceType;

#define IS_CLOCK_SOURCE_PARA(SYSCLK) (((SYSCLK) == SYSCLK_SRC_INTERNAL_OSC) || \
                                      ((SYSCLK) == SYSCLK_SRC_EXTERNAL_OSC))

/*!
 * @brief System clock divide enumeration.
 */
typedef enum
{
    SYSCLK_DIVIDER_1 = 0,
    SYSCLK_DIVIDER_2,
    SYSCLK_DIVIDER_4,
    SYSCLK_DIVIDER_16
} SYSCLK_DividerType;

#define IS_SYSCLK_DIVIDER_PARA(DIVIDER) (((DIVIDER) == SYSCLK_DIVIDER_1) || \
                                         ((DIVIDER) == SYSCLK_DIVIDER_2) || \
                                         ((DIVIDER) == SYSCLK_DIVIDER_4) || \
                                         ((DIVIDER) == SYSCLK_DIVIDER_16))

/*!
 * @brief APBCLK clock divider enumeration.
 */
typedef enum
{
    APBCLK_DIVIDER_1 = 0,
    APBCLK_DIVIDER_2,
    APBCLK_DIVIDER_3,
    APBCLK_DIVIDER_4
} APBCLK_DividerType;

#define IS_APBCLK_DIVIDER_PARA(DIVIDER) (((DIVIDER) == APBCLK_DIVIDER_1) || \
                                         ((DIVIDER) == APBCLK_DIVIDER_2) || \
                                         ((DIVIDER) == APBCLK_DIVIDER_3) || \
                                         ((DIVIDER) == APBCLK_DIVIDER_4))

/* ==========================================  Variables  =========================================== */

/* ====================================  Functions declaration  ===================================== */
/*!
 * @brief Enale the module clock.
 *
 * @param[in] module: CKGEN_ClockType, value can be
 *                   - CLK_UART0
 *                   - CLK_UART1
 *                   - CLK_SPI0
 *                   - CLK_I2C0
 *                   - CLK_PWDT0
 *                   - CLK_PWM0
 *                   - CLK_PWM1
 *                   - CLK_PWM2
 *                   - CLK_TIMER
 *                   - CLK_RTC
 *                   - CLK_GPIO
 *                   - CLK_WDG
 *                   - CLK_CTU
 *                   - CLK_ADC0
 *                   - CLK_ACMP0
 * @param[in] enable: enable state
 *                   - ENABLE
 *                   - DISABLE
 * @return none
 */
void CKGEN_Enable(CKGEN_ClockType module, ACTION_Type enable);

/*!
 * @brief Do soft reset for the module.
 *
 * @param[in] module: the module to do soft reset, value can be
 *                   - SRST_UART0
 *                   - SRST_UART1
 *                   - SRST_SPI0
 *                   - SRST_I2C0
 *                   - SRST_PWDT0
 *                   - SRST_PWM0
 *                   - SRST_PWM1
 *                   - SRST_PWM2
 *                   - SRST_TIMER
 *                   - SRST_RTC
 *                   - SRST_GPIO
 *                   - SRST_WDG
 *                   - SRST_CTU
 *                   - SRST_ADC0
 *                   - SRST_ACMP0
 *                   - SRST_ANA_REG
 * @param[in] active: active state
 *                   - ENABLE
 *                   - DISABLE
 * @return none
 */
void CKGEN_SoftReset(CKGEN_SoftResetType module, ACTION_Type active);

/*!
 * @brief Set the system clock source.
 *
 * @param[in] clockSource: system clock source, value can be
 *                        - SYSCLK_SRC_INTERNAL_OSC
 *                        - SYSCLK_SRC_EXTERNAL_OSC
 * @return none
 */
void CKGEN_SetSysclkSrc(SYSTEM_ClockSourceType clockSource);

/*!
 * @brief Set the sysclck divider.
 *
 * @param[in] div: system clock divider set, value can be
 *                - SYSCLK_DIVIDER_1
 *                - SYSCLK_DIVIDER_2
 *                - SYSCLK_DIVIDER_4
 *                - SYSCLK_DIVIDER_16
 * @return none
 */
void CKGEN_SetSysclkDiv(SYSCLK_DividerType div);

/*!
 * @brief Set the APB clock divider.
 *
 * @param[in] div: apb clock divider set, value can be
 *                - APBCLK_DIVIDER_1
 *                - APBCLK_DIVIDER_2
 *                - APBCLK_DIVIDER_3
 *                - APBCLK_DIVIDER_4
 * @return none
 */
void CKGEN_SetAPBClockDivider(APBCLK_DividerType div);

/*!
 * @brief Enable/Disable XOSC monitor.
 *
 * @param[in] enable: enable state
 *                   - ENABLE
 *                   - DISABLE
 * @return none
 */
void CKGEN_EnableXOSCMonitor(ACTION_Type enable);

#ifdef __cplusplus
}
#endif

#endif /* _AC780X_CKGEN_H */

/* =============================================  EOF  ============================================== */
