/*
 * Copyright Statement:
 *
 * This software/firmware and related documentation ("AutoChips Software") are
 * protected under relevant copyright laws. The information contained herein is
 * confidential and proprietary to AutoChips Inc. and/or its licensors. Without
 * the prior written permission of AutoChips inc. and/or its licensors, any
 * reproduction, modification, use or disclosure of AutoChips Software, and
 * information contained herein, in whole or in part, shall be strictly
 * prohibited.
 *
 * AutoChips Inc. (C) 2020. All rights reserved.
 *
 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("AUTOCHIPS SOFTWARE")
 * RECEIVED FROM AUTOCHIPS AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
 * ON AN "AS-IS" BASIS ONLY. AUTOCHIPS EXPRESSLY DISCLAIMS ANY AND ALL
 * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
 * NONINFRINGEMENT. NEITHER DOES AUTOCHIPS PROVIDE ANY WARRANTY WHATSOEVER WITH
 * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
 * INCORPORATED IN, OR SUPPLIED WITH THE AUTOCHIPS SOFTWARE, AND RECEIVER AGREES
 * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
 * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
 * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN AUTOCHIPS
 * SOFTWARE. AUTOCHIPS SHALL ALSO NOT BE RESPONSIBLE FOR ANY AUTOCHIPS SOFTWARE
 * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND AUTOCHIPS'S
 * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE AUTOCHIPS SOFTWARE
 * RELEASED HEREUNDER WILL BE, AT AUTOCHIPS'S OPTION, TO REVISE OR REPLACE THE
 * AUTOCHIPS SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
 * CHARGE PAID BY RECEIVER TO AUTOCHIPS FOR SUCH AUTOCHIPS SOFTWARE AT ISSUE.
 *
 * @file     AC780x.h
 * @brief    CMSIS HeaderFile
 * @version  1.0
 * @date     09. November 2020
 * @note     Generated by SVDConv V3.3.27 on Monday, 09.11.2020 17:17:07
 *           from File 'ac780x.svd',
 *           last modified on Monday, 09.11.2020 09:14:20
 */



/** @addtogroup AutoChips
  * @{
  */


/** @addtogroup AC780x
  * @{
  */


#ifndef _AC780X_H
#define _AC780X_H

#ifdef __cplusplus
extern "C" {
#endif


/** @addtogroup Configuration_of_CMSIS
  * @{
  */



/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

typedef enum {
/* =======================================  ARM Cortex-M0+ Specific Interrupt Numbers  ======================================= */
  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
/* ===========================================  AC780x Specific Interrupt Numbers  =========================================== */
  PWDT0_IRQn                =   0,              /*!< 0  PWDT0 interrupt                                                        */
  PWDT1_IRQn                =   1,              /*!< 1  PWDT1 interrupt                                                        */
  PWM0_IRQn                 =   2,              /*!< 2  PWM0 interrupt                                                         */
  PWM1_IRQn                 =   3,              /*!< 3  PWM1 interrupt                                                         */
  ACMP0_IRQn                =   4,              /*!< 4  ACMP0 interrupt                                                        */
  UART0_IRQn                =   5,              /*!< 5  UART0 interrupt                                                        */
  UART1_IRQn                =   6,              /*!< 6  UART1 interrupt                                                        */
  UART2_IRQn                =   7,              /*!< 7  UART2 interrupt                                                        */
  WDG_IRQn                  =   8,              /*!< 8  WDG interrupt                                                          */
  SPI0_IRQn                 =   9,              /*!< 9  SPI0 interrupt                                                         */
  SPI1_IRQn                 =  10,              /*!< 10 SPI1 interrupt                                                         */
  I2C0_IRQn                 =  11,              /*!< 11 I2C0 Interrupt                                                         */
  I2C1_IRQn                 =  12,              /*!< 12 I2C1 Interrupt                                                         */
  DMA0_CHANNEL0_IRQn        =  13,              /*!< 13 DMA0 channel 0 interrupt                                               */
  DMA0_CHANNEL1_IRQn        =  14,              /*!< 14 DMA0 channel 1 interrupt                                               */
  DMA0_CHANNEL2_IRQn        =  15,              /*!< 15 DMA0 channel 2 interrupt                                               */
  DMA0_CHANNEL3_IRQn        =  16,              /*!< 16 DMA0 channel 3 interrupt                                               */
  TIMER_CHANNEL0_IRQn       =  17,              /*!< 17 TIMER channel 0 interrupt                                              */
  TIMER_CHANNEL1_IRQn       =  18,              /*!< 18 TIMER channel 1 interrupt                                              */
  TIMER_CHANNEL2_IRQn       =  19,              /*!< 19 TIMER channel 2 interrupt                                              */
  TIMER_CHANNEL3_IRQn       =  20,              /*!< 20 TIMER channel 3 interrupt                                              */
  RTC_IRQn                  =  21,              /*!< 21 RTC Interrupt                                                          */
  PVD_IRQn                  =  22,              /*!< 22 PVD Interrupt                                                          */
  SPM_IRQn                  =  23,              /*!< 23 SPM interrupt                                                          */
  CAN0_IRQn                 =  24,              /*!< 24 CAN0 interrupt                                                         */
  ADC0_IRQn                 =  25,              /*!< 25 ADC0 interrupt                                                         */
  ECC_SRAM_IRQn             =  26,              /*!< 26 ECC SRAM interrupt                                                     */
  EXTI0_IRQn                =  27,              /*!< 27 GPIOx PIN0 external interrupt                                          */
  EXTI1_IRQn                =  28,              /*!< 28 GPIOx PIN1 external interrupt                                          */
  EXTI2_IRQn                =  29,              /*!< 29 GPIOx PIN2 external interrupt                                          */
  EXTI3_8_IRQn              =  30,              /*!< 30 GPIOx PIN3~8 external interrupt                                        */
  EXTI9_15_IRQn             =  31               /*!< 31 GPIOx PIN9~15 external interrupt                                       */
} IRQn_Type;


/**
* @brief setting bits macro.
*/
#ifndef SET_BIT32
  #define SET_BIT32(reg, mask)              ((reg) |= (uint32_t)(mask))
#endif

/**
* @brief clearing bits macro.
*/
#ifndef CLEAR_BIT32
  #define CLEAR_BIT32(reg, mask)            ((reg) &= (~((uint32_t)(mask))))
#endif

/**
* @brief read bits macro.
*/
#ifndef READ_BIT32
  #define READ_BIT32(reg, mask)             ((reg) & ((uint32_t)(mask)))
#endif

/**
* @brief write register macro.
*/
#ifndef WRITE_REG32
  #define WRITE_REG32(reg, value)           ((reg) = (uint32_t)(value))
#endif

/**
* @brief clear bits and set with new value
*/
#ifndef MODIFY_REG32
  #define MODIFY_REG32(reg, mask, pos, value)  (WRITE_REG32((reg), (((reg) & (~((uint32_t)mask))) | (((uint32_t)value) << pos))))
#endif

/**
* @brief read 32 bits memory macro.
*/
#ifndef READ_MEM32
  #define READ_MEM32(address)               (*(volatile uint32_t*)(address))
#endif

/**
* @brief write 32 bits memory macro.
*/
#ifndef WRITE_MEM32
  #define WRITE_MEM32(address, value)       ((*(volatile uint32_t*)(address))= (uint32_t)(value))
#endif

/**
* @brief clear bits and set with new value for memory.
*/
#ifndef MODIFY_MEM32
  #define MODIFY_MEM32(address, mask, pos, value)   (WRITE_MEM32((address), ((READ_MEM32(address) & (~((uint32_t)mask))) | (((uint32_t)value) << pos))))
#endif

#include <stdint.h>
#include <stdio.h>

/**
* @brief global enumeration.
*/
typedef enum {FALSE = 0, TRUE = !FALSE} BOOL_Type;

typedef enum {DISABLE = 0, ENABLE = !DISABLE} ACTION_Type;

typedef enum {ERROR = 0, SUCCESS = !ERROR} ERROR_Type;

typedef void (*DeviceCallback_Type)(void *device, uint32_t wpara, uint32_t lpara);

/* =========================================================================================================================== */
/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/* ==========================  Configuration of the ARM Cortex-M0+ Processor and Core Peripherals  =========================== */
#define __CM0PLUS_REV                 0x0001U   /*!< CM0PLUS Core Revision r0p1                                                */
#define __NVIC_PRIO_BITS               2        /*!< Number of Bits used for Priority Levels                                   */
#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
#define __VTOR_PRESENT                 1        /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
#define __MPU_PRESENT                  1        /*!< MPU present                                                               */
#define __FPU_PRESENT                  0        /*!< FPU present                                                               */


/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm0plus.h"                       /*!< ARM Cortex-M0+ processor and core peripherals                             */
//#include "system_ac780x.h"                      /*!< AC780x System                                                             */

#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __IM   __I
#endif
#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __OM   __O
#endif
#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
  #define __IOM  __IO
#endif


/* =========================================================================================================================== */
/* ================                            Device Specific Peripheral Section                             ================ */
/* =========================================================================================================================== */

/* ---------------------------------------------   section using anonymous unions  ------------------------------------------- */
#if defined(__CC_ARM)
  #pragma anon_unions
#elif defined(CCARM__)
  #pragma language=extended
#elif defined (__ICCARM__)
/* anonymous unions are enabled by default */
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
  #pragma warning 586
#else
  #warning Not supported compiler type
#endif


/** @addtogroup Device_Peripheral_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                           CKGEN                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Clock Generator (CKGEN)
  */

typedef struct {                                /*!< (@ 0x40000000) CKGEN Structure                                            */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000000) CKGEN Control Register                                     */
  __IOM uint32_t  PERI_CLK_EN_0;                /*!< (@ 0x00000004) Periph Clock Enable Control 0                              */
  __IOM uint32_t  PERI_CLK_EN_1;                /*!< (@ 0x00000008) Periph Clock Enable Control 1                              */
  __IOM uint32_t  RESET_CTRL;                   /*!< (@ 0x0000000C) MCU Reset Control                                          */
  __IOM uint32_t  RESET_STATUS;                 /*!< (@ 0x00000010) MCU Reset Status                                           */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PERI_SFT_RST0;                /*!< (@ 0x00000018) Periph Software Reset Control 0                            */
  __IOM uint32_t  PERI_SFT_RST1;                /*!< (@ 0x0000001C) Periph Software Reset Control 1                            */
  __IM  uint32_t  RESERVED1[8732];
  __IOM uint32_t  SYSPLL1_CFG0;                 /*!< (@ 0x00008890) MCU System PLL Config 0                                    */
} CKGEN_Type;                                   /*!< Size = 34964 (0x8894)                                                     */



/* =========================================================================================================================== */
/* ================                                            SPM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief System Power Manage (SPM)
  */

typedef struct {                                /*!< (@ 0x40008000) SPM Structure                                              */
  __IOM uint32_t  PWR_MGR_CFG0;                 /*!< (@ 0x00000000) Power Manage Config Register 0                             */
  __IOM uint32_t  PWR_MGR_CFG1;                 /*!< (@ 0x00000004) Power Manage Config Register 1                             */
  __IM  uint32_t  RESERVED;
  __IM  uint32_t  PERIPH_SLEEP_ACK_STATUS;      /*!< (@ 0x0000000C) Periph Sleep Ack Status Set                                */
  __IOM uint32_t  EN_PERIPH_SLEEP_ACK;          /*!< (@ 0x00000010) Enable Periph Sleep Ack                                    */
  __IOM uint32_t  EN_PERIPH_WAKEUP;             /*!< (@ 0x00000014) Enable Periph Sleep Ack                                    */
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  WAKEUP_IRQ_STATUS;            /*!< (@ 0x0000001C) SPM Wakeup IRQ Status                                      */
} SPM_Type;                                     /*!< Size = 32 (0x20)                                                          */



/* =========================================================================================================================== */
/* ================                                           GPIO                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief General Purpose Input/Output (GPIO)
  */

typedef struct {                                /*!< (@ 0x20080000) GPIO Structure                                             */
  __IOM uint32_t  CR;                           /*!< (@ 0x00000000) GPIOx Configuration Register                               */
  __IM  uint32_t  IDR;                          /*!< (@ 0x00000004) GPIO Input Data Register                                   */
  __IOM uint32_t  ODR;                          /*!< (@ 0x00000008) GPIO Output Data Register                                  */
  __IOM uint32_t  BSRR;                         /*!< (@ 0x0000000C) GPIO Bit Set, Reset Register                               */
  __IOM uint32_t  BRR;                          /*!< (@ 0x00000010) GPIO Bit Reset Register                                    */
  __IM  uint32_t  RESERVED;
  __IOM uint32_t  PD;                           /*!< (@ 0x00000018) GPIO Pull Down Register                                    */
  __IOM uint32_t  PU;                           /*!< (@ 0x0000001C) GPIO Pull Up Register                                      */
  __IOM uint32_t  E4_E2;                        /*!< (@ 0x00000020) GPIO E4_E2 Register                                        */
} GPIO_Type;                                    /*!< Size = 36 (0x24)                                                          */

#define GPIO_INSTANCE_MAX                (3UL)  /*!< Number of instances of the GPIO module                                    */

/* =========================================================================================================================== */
/* ================                                           PMUX                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief PinMux Function (PMUX)
  */

typedef struct {                                /*!< (@ 0x20080140) PMUX Structure                                             */
  __IOM uint32_t  PINMUX0;                      /*!< (@ 0x00000000) PinMux Function Register                                   */
  __IOM uint32_t  PINMUX1;                      /*!< (@ 0x00000004) PinMux Function Register                                   */
  __IOM uint32_t  PINMUX2;                      /*!< (@ 0x00000008) PinMux Function Register                                   */
  __IOM uint32_t  PINMUX3;                      /*!< (@ 0x0000000C) PinMux Function Register                                   */
  __IOM uint32_t  PINMUX4;                      /*!< (@ 0x00000010) PinMux Function Register                                   */
} PMUX_Type;                                    /*!< Size = 20 (0x14)                                                          */

#define PMUX_INSTANCE_MAX                (1UL)  /*!< Number of instances of the PMUX module                                    */

/* =========================================================================================================================== */
/* ================                                           EXTI                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief External Interrupt (EXTI)
  */

typedef struct {                                /*!< (@ 0x20080160) EXTI Structure                                             */
  __IOM uint32_t  PR;                           /*!< (@ 0x00000000) EXTI Pending Register                                      */
  __IOM uint32_t  IMR;                          /*!< (@ 0x00000004) EXTI Mask Register                                         */
  __IOM uint32_t  RTSR;                         /*!< (@ 0x00000008) EXTI Rasing edge Register                                  */
  __IOM uint32_t  FTSR;                         /*!< (@ 0x0000000C) EXTI Falling edge Register                                 */
  __IOM uint32_t  EXTICR0;                      /*!< (@ 0x00000010) EXTI Control Register                                      */
  __IOM uint32_t  EXTICR1;                      /*!< (@ 0x00000014) EXTI Control Register                                      */
  __IOM uint32_t  EXTICR2;                      /*!< (@ 0x00000018) EXTI Control Register                                      */
  __IOM uint32_t  EXTICR3;                      /*!< (@ 0x0000001C) EXTI Control Register                                      */
} EXTI_Type;                                    /*!< Size = 32 (0x20)                                                          */

#define EXTI_INSTANCE_MAX                (1UL)  /*!< Number of instances of the EXTI module                                    */

/* =========================================================================================================================== */
/* ================                                           CAN                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief Controller Area Network (CAN)
  */

#define CAN_BUF_LENGTH (64 / 4)                 /*!< CAN buffer length                                                         */

/**
  * @brief CAN receive buffer register define structure
  */

typedef struct
{
    __IO uint32_t  ID_ESI;                      /*!< [0:28]: Identifier (ID), [31]: Error state indicator (ESI)                */
    __IO uint32_t  RXCTRL;                      /*!< [0:3]: Data length code (DLC), [4]: Bit rate switch (BRS)                 */
                                                /*!< [5]: FD format indicator (FDF),[6]: Remote transmission request (RTR)     */
                                                /*!< [7]: Identifier extension (IDE),[12]: For lookback mode (Tx)              */
                                                /*!< [13:15]: Kind of error                                                    */
    __IO uint32_t  DATA[CAN_BUF_LENGTH];        /*!< Buffer data                                                               */
    __IO uint32_t  RTS[2];                      /*!< Receive time stamps                                                       */
} CAN_RbufType;

/**
  * @brief CAN transmit buffer register define structure
  */

typedef struct
{
    __IO uint32_t  ID_TTSEN;                    /*!< [0:28]: Identifier (ID), [31]: Transmit time-stamp enable (TISEN)         */
    __IO uint32_t  TXCTRL;                      /*!< [0:3]: Data length code (DLC), [4]: Bit rate switch (BRS)                 */
                                                /*!< [5]: FD format indicator (FDF),[6]: Remote transmission request (RTR)     */
                                                /*!< [7]: Identifier extension (IDE)                                           */
    __IO uint32_t  DATA[CAN_BUF_LENGTH];        /*!< Buffer data                                                               */
} CAN_TbufType;

typedef struct {                                /*!< (@ 0x40007800) CAN Structure                                              */
  __IOM CAN_RbufType  RBUF;                     /*!< (@ 0x00000000) Receive buffer                                             */
  __IOM CAN_TbufType  TBUF;                     /*!< (@ 0x00000050) Transmit buffer                                            */
  __IM  uint32_t      TTS[2];                   /*!< (@ 0x00000098) Transmission time stamp                                    */
  __IOM uint32_t      CTRL0;                    /*!< (@ 0x000000A0) Config state and transmit/receive control register 0       */
  __IOM uint32_t      CTRL1;                    /*!< (@ 0x000000A4) CAN interrupt enable/disable and flag control
                                                                    register 1                                                 */
  __IOM uint32_t      SBITRATE;                 /*!< (@ 0x000000A8) Normat CAN baudrate configuration register                 */
  __IOM uint32_t      FBITRATE;                 /*!< (@ 0x000000AC) FAST CAN(CAN_FD) baudrate configuration register           */
  __IOM uint32_t      ERRINFO;                  /*!< (@ 0x000000B0) CAN error type and transmit/receive error conunter
                                                                    register                                                   */
  __IOM uint32_t      ACFCTRL;                  /*!< (@ 0x000000B4) Acceptance Filter Control Register                         */
  __IOM uint32_t      ACF;                      /*!< (@ 0x000000B8) Acceptance Code Register                                   */
  __IOM uint32_t      VERSION;                  /*!< (@ 0x000000BC) Version Information Register 0                             */
} CAN_Type;                                     /*!< Size = 192 (0xc0)                                                         */

#define CAN_INSTANCE_MAX                (1UL)   /*!< Number of instances of the CAN module                                     */

/* =========================================================================================================================== */
/* ================                                           UART                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Universal Asynchronous Receiver/Transmitter (UART)
  */

typedef struct {                                /*!< (@ 0x40018000) UART Structure                                             */
  __IOM uint32_t  RBR;                          /*!< (@ 0x00000000) RX/TX Data Register                                        */
  __IOM uint32_t  DIV_L;                        /*!< (@ 0x00000004) Divisor low 8 bits register                                */
  __IOM uint32_t  DIV_H;                        /*!< (@ 0x00000008) Divisor high 8 bits register                               */
  __IOM uint32_t  LCR0;                         /*!< (@ 0x0000000C) uart control register 0                                    */
  __IOM uint32_t  LCR1;                         /*!< (@ 0x00000010) uart control register 1                                    */
  __IOM uint32_t  FCR;                          /*!< (@ 0x00000014) FIFO Control Register                                      */
  __IOM uint32_t  EFR;                          /*!< (@ 0x00000018) hardware flow control register                             */
  __IOM uint32_t  IER;                          /*!< (@ 0x0000001C) Interrupt Enable register                                  */
  __IOM uint32_t  LSR0;                         /*!< (@ 0x00000020) Line Status Register 0                                     */
  __IOM uint32_t  LSR1;                         /*!< (@ 0x00000024) Line Status Register 1                                     */
  __IOM uint32_t  SMP_CNT;                      /*!< (@ 0x00000028) uart sample counter register                               */
  __IM  uint32_t  RESERVED[2];
  __IOM uint32_t  GUARD;                        /*!< (@ 0x00000034) uart guard time register                                   */
  __IM  uint32_t  RESERVED1;
  __IOM uint32_t  SLEEP_EN;                     /*!< (@ 0x0000003C) uart sleep enable register                                 */
  __IOM uint32_t  DMA_EN;                       /*!< (@ 0x00000040) uart DMA enable register                                   */
  __IOM uint32_t  DIV_FRAC;                     /*!< (@ 0x00000044) Uart Fractional Divider Address                            */
  __IM  uint32_t  RESERVED2;
  __IOM uint32_t  RS485CR;                      /*!< (@ 0x0000004C) Uart RS485 control register                                */
  __IM  uint32_t  RESERVED3;
  __IOM uint32_t  CNTR;                         /*!< (@ 0x00000054) Uart Counter time delay in RS485 mode                      */
  __IOM uint32_t  IDLE;                         /*!< (@ 0x00000058) Uart IDLE register                                         */
  __IOM uint32_t  LINCR;                        /*!< (@ 0x0000005C) LIN Control register                                       */
  __IOM uint32_t  BRKLGH;                       /*!< (@ 0x00000060) LIN Break Length Select Register                           */
} UART_Type;                                    /*!< Size = 100 (0x64)                                                         */

#define UART_INSTANCE_MAX               (3UL)   /*!< Number of instances of the UART module                                    */

/* =========================================================================================================================== */
/* ================                                           I2C                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief Inter-Integrated Circuit (I2C)
  */

typedef struct {                                /*!< (@ 0x4000E000) I2C Structure                                              */
  __IOM uint32_t  ADDR0;                        /*!< (@ 0x00000000) Address Register 0                                         */
  __IOM uint32_t  ADDR1;                        /*!< (@ 0x00000004) Address register 1                                         */
  __IOM uint32_t  SAMPLE_CNT;                   /*!< (@ 0x00000008) SAMPLE_CNT Register                                        */
  __IOM uint32_t  STEP_CNT;                     /*!< (@ 0x0000000C) STEP_CNT Register                                          */
  __IOM uint32_t  CTRL0;                        /*!< (@ 0x00000010) Control Register 0                                         */
  __IOM uint32_t  CTRL1;                        /*!< (@ 0x00000014) Control Register 1                                         */
  __IOM uint32_t  CTRL2;                        /*!< (@ 0x00000018) Control Register 2                                         */
  __IOM uint32_t  CTRL3;                        /*!< (@ 0x0000001C) Control Register 3                                         */
  __IOM uint32_t  STATUS0;                      /*!< (@ 0x00000020) Status Register 0                                          */
  __IOM uint32_t  STATUS1;                      /*!< (@ 0x00000024) Status Register 1                                          */
  __IOM uint32_t  DGLCFG;                       /*!< (@ 0x00000028) Deglitch Configuration Register                            */
  __IOM uint32_t  DATA;                         /*!< (@ 0x0000002C) Data Register                                              */
  __IOM uint32_t  STARTSTOP;                    /*!< (@ 0x00000030) START_STOP Register                                        */
} I2C_Type;                                     /*!< Size = 52 (0x34)                                                          */

#define I2C_INSTANCE_MAX                (2UL)   /*!< Number of instances of the I2C module                                     */

/* =========================================================================================================================== */
/* ================                                           SPI                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief Serial Peripheral Interface (SPI)
  */

typedef struct {                                /*!< (@ 0x4000C000) SPI Structure                                              */
  __IOM uint32_t  CFG0;                         /*!< (@ 0x00000000) SPI Configuration Register 0                               */
  __IOM uint32_t  CFG1;                         /*!< (@ 0x00000004) SPI Configuration Register 1                               */
  __IOM uint32_t  CMD;                          /*!< (@ 0x00000008) SPI Command Register                                       */
  __IOM uint32_t  STATUS;                       /*!< (@ 0x0000000C) SPI Status Register                                        */
  __IOM uint32_t  DATA;                         /*!< (@ 0x00000010) SPI Data Register                                          */
  __IOM uint32_t  CFG2;                         /*!< (@ 0x00000014) SPI configuration register 2                               */
} SPI_Type;                                     /*!< Size = 24 (0x18)                                                          */

#define SPI_INSTANCE_MAX                (2UL)   /*!< Number of instances of the SPI module                                     */

/* =========================================================================================================================== */
/* ================                                           ADC                                             ================ */
/* =========================================================================================================================== */

#define ADC_INJECT_NUM                  (4UL)


/**
  * @brief Analog to Digital Converter (ADC)
  */

typedef struct {                                /*!< (@ 0x40003000) ADC Structure                                              */
  __IOM uint32_t  STR;                          /*!< (@ 0x00000000) ADC status Register                                        */
  __IOM uint32_t  CTRL0;                        /*!< (@ 0x00000004) ADC Control Register 0                                     */
  __IOM uint32_t  CTRL1;                        /*!< (@ 0x00000008) ADC Control Register 1                                     */
  __IOM uint32_t  SPT0;                         /*!< (@ 0x0000000C) ADC Sample time setting register 0                         */
  __IOM uint32_t  SPT1;                         /*!< (@ 0x00000010) ADC Sample time setting register 1                         */
  __IOM uint32_t  IOFR[ADC_INJECT_NUM];         /*!< (@ 0x00000014) ADC Injection Group Offset Register                        */
  __IOM uint32_t  AMOHR;                        /*!< (@ 0x00000024) AMO High threshold and offset register                     */
  __IOM uint32_t  AMOLR;                        /*!< (@ 0x00000028) AMO Low threshold and offset register                      */
  __IOM uint32_t  RSQR0;                        /*!< (@ 0x0000002C) ADC regular group sequence configure register 0            */
  __IOM uint32_t  RSQR1;                        /*!< (@ 0x00000030) ADC regular group sequence configure register 1            */
  __IOM uint32_t  RSQR2;                        /*!< (@ 0x00000034) ADC regular group sequence configure register 2            */
  __IOM uint32_t  ISQR;                         /*!< (@ 0x00000038) ADC injection group sequence configure register            */
  __IM  uint32_t  IDR[ADC_INJECT_NUM];          /*!< (@ 0x0000003C) ADC Injection Group data Register                          */
  __IM  uint32_t  RDR;                          /*!< (@ 0x0000004C) ADC Regular Group data Register                            */
} ADC_Type;                                     /*!< Size = 80 (0x50)                                                          */

#define ADC_INSTANCE_MAX                (1UL)   /*!< Number of instances of the ADC module                                     */
#define ADC_CHANNEL_MAX                 (12UL)  /*!< Number of channel of the ADC                                              */

/* =========================================================================================================================== */
/* ================                                        ACMP_ANACFG                                        ================ */
/* =========================================================================================================================== */


/**
  * @brief ACMP Analog Config (ACMP_ANACFG)
  */

typedef struct {                                /*!< (@ 0x40008820) ACMP_ANACFG Structure                                      */
  __IOM uint32_t  CFG0;                         /*!< (@ 0x00000000) ACMP analog config register 0                              */
} ACMP_ANACfgType;                              /*!< Size = 4 (0x4)                                                            */



/* =========================================================================================================================== */
/* ================                                           ACMP                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Analog comparator (ACMP)
  */

typedef struct {                                /*!< (@ 0x40005000) ACMP Structure                                             */
  __IOM uint32_t  CR0;                          /*!< (@ 0x00000000) ACMP Configuration Register 0                              */
  __IOM uint32_t  CR1;                          /*!< (@ 0x00000004) ACMP Configuration Register 1                              */
  __IOM uint32_t  CR2;                          /*!< (@ 0x00000008) ACMP configuration register 2                              */
  __IOM uint32_t  CR3;                          /*!< (@ 0x0000000C) ACMP configuration register 3                              */
  __IOM uint32_t  CR4;                          /*!< (@ 0x00000010) ACMP configuration register 4                              */
  __IM  uint32_t  DR;                           /*!< (@ 0x00000014) ACMP data output register 0                                */
  __IOM uint32_t  SR;                           /*!< (@ 0x00000018) ACMP status register 0                                     */
  __IOM uint32_t  FD;                           /*!< (@ 0x0000001C) ACMP polling frequency divider register                    */
  __IOM uint32_t  OPA;                          /*!< (@ 0x00000020) ACMP hall output A set register                            */
  __IOM uint32_t  OPB;                          /*!< (@ 0x00000024) ACMP hall output B set register                            */
  __IOM uint32_t  OPC;                          /*!< (@ 0x00000028) ACMP hall output C set register                            */
  __IOM uint32_t  DACSR;                        /*!< (@ 0x0000002C) ACMP DAC reference select register                         */
} ACMP_Type;                                    /*!< Size = 48 (0x30)                                                          */

#define ACMP_INSTANCE_MAX               (1UL)   /*!< Number of instances of the ACMP module                                    */

/* =========================================================================================================================== */
/* ================                                           PWM                                             ================ */
/* =========================================================================================================================== */


/**
  * @brief Pulse Width Modulation (PWM)
  */

#define PWM_CHANNEL_MAX                 (8UL)   /*!< Number of channel of the PWM module                                       */

typedef struct {                                /*!< (@ 0x40013000) PWM Structure                                              */
  __IOM uint32_t  INIT;                         /*!< (@ 0x00000000) PWM Initialize, Include Clock and Prescale Setting         */
  __IOM uint32_t  CNT;                          /*!< (@ 0x00000004) PWM Counter Current Count Value                            */
  __IOM uint32_t  MCVR;                         /*!< (@ 0x00000008) PWM Counter Max Count Value Register                       */
    struct {
  __IOM uint32_t  CHSCR;                        /*!< (@ 0x0000000C) Channel (n) Status And Control Register                    */
  __IOM uint32_t  CHV;                          /*!< (@ 0x00000010) Channel (n) Value                                          */
  } CHANNELS[PWM_CHANNEL_MAX];
  __IOM uint32_t  CNTIN;                        /*!< (@ 0x0000004C) Counter Initial Value                                      */
  __IOM uint32_t  STR;                          /*!< (@ 0x00000050) Status Register                                            */
  __IOM uint32_t  FUNCSEL;                      /*!< (@ 0x00000054) PWM Features(Functions) Mode Selection Register            */
  __IOM uint32_t  SYNC;                         /*!< (@ 0x00000058) Synchronization                                            */
  __IOM uint32_t  OUTINIT;                      /*!< (@ 0x0000005C) Initial Value For Channels Output                          */
  __IOM uint32_t  OMCR;                         /*!< (@ 0x00000060) Output Mask Control Register                               */
  __IOM uint32_t  MODESEL;                      /*!< (@ 0x00000064) PWM Function Mode Selection                                */
  __IOM uint32_t  DTSET;                        /*!< (@ 0x00000068) Deadtime Setting Register                                  */
  __IOM uint32_t  EXTTRIG;                      /*!< (@ 0x0000006C) PWM External Trigger                                       */
  __IOM uint32_t  CHOPOLCR;                     /*!< (@ 0x00000070) Channel Output Polarity Register                           */
  __IOM uint32_t  FDSR;                         /*!< (@ 0x00000074) Fault Detect Status Register                               */
  __IOM uint32_t  CAPFILTER;                    /*!< (@ 0x00000078) Input Capture Filter Control                               */
  __IOM uint32_t  FFAFER;                       /*!< (@ 0x0000007C) Fault Filter and Fault Enable Register                     */
  __IOM uint32_t  QDI;                          /*!< (@ 0x00000080) Quadrature Decoder Interface Configuration Register        */
  __IOM uint32_t  CONF;                         /*!< (@ 0x00000084) Configuration                                              */
  __IOM uint32_t  FLTPOL;                       /*!< (@ 0x00000088) PWM Fault Input Polarity                                   */
  __IOM uint32_t  SYNCONF;                      /*!< (@ 0x0000008C) Synchronization Configuration                              */
  __IOM uint32_t  INVCR;                        /*!< (@ 0x00000090) PWM Inverse Control Register                               */
  __IOM uint32_t  CHOSWCR;                      /*!< (@ 0x00000094) PWM CHannel Output Software Control Register               */
} PWM_Type;                                     /*!< Size = 152 (0x98)                                                         */

#define PWM_INSTANCE_MAX                (2UL)   /*!< Number of instances of the PWM module                                     */

/* =========================================================================================================================== */
/* ================                                           PWDT                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Pulse Width Detection Timer (PWDT)
  */

typedef struct {                                /*!< (@ 0x40017000) PWDT Structure                                             */
  __IOM uint32_t  INIT0;                        /*!< (@ 0x00000000) PWDT Initialize Register 0                                 */
  __IM  uint32_t  NPW;                          /*!< (@ 0x00000004) Negative Pulse Width                                       */
  __IOM uint32_t  INIT1;                        /*!< (@ 0x00000008) Pulse Width Detection Timer Initialize Register 1          */
} PWDT_Type;                                    /*!< Size = 12 (0xc)                                                           */

#define PWDT_INSTANCE_MAX               (2UL)   /*!< Number of instances of the PWDT module                                    */

/* =========================================================================================================================== */
/* ================                                        TIMER_CTRL                                         ================ */
/* =========================================================================================================================== */


/**
  * @brief Timer Control (TIMER_CTRL)
  */

typedef struct {                                /*!< (@ 0x40011000) TIMER_CTRL Structure                                       */
  __IOM uint32_t  MCR;                          /*!< (@ 0x00000000) Timer Module Control Regitser                              */
} TIMER_CtrlType;                               /*!< Size = 4 (0x4)                                                            */



/* =========================================================================================================================== */
/* ================                                      TIMER_CHANNEL                                        ================ */
/* =========================================================================================================================== */


/**
  * @brief Timer channel  (TIMER_CHANNEL)
  */

typedef struct {                                /*!< (@ 0x40011100) TIMER_CHANNEL Structure                                    */
  __IOM uint32_t  LDVAL;                        /*!< (@ 0x00000000) Timer Load Value Register                                  */
  __IM  uint32_t  CVAL;                         /*!< (@ 0x00000004) Timer Current Count Value Register                         */
  __IOM uint32_t  INIT;                         /*!< (@ 0x00000008) Timer Initialize Control Register                          */
  __IOM uint32_t  TF;                           /*!< (@ 0x0000000C) Timer Flag Register                                        */
} TIMER_ChannelType;                            /*!< Size = 16 (0x10)                                                          */

#define TIMER_CHANNEL_MAX               (4UL)   /*!< Number of channel of the TIMER                                            */

/* =========================================================================================================================== */
/* ================                                            CTU                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Connect Module Unit (CTU)
  */

typedef struct {                                /*!< (@ 0x40016000) CTU Structure                                              */
  __IOM uint32_t  CONFIG0;                      /*!< (@ 0x00000000) CTU Configuration Register 0                               */
  __IOM uint32_t  CONFIG1;                      /*!< (@ 0x00000004) CTU Configuration Register 1                               */
} CTU_Type;                                     /*!< Size = 8 (0x8)                                                            */



/* =========================================================================================================================== */
/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief DMA All Channnels Share The Registers (DMA)
  */

typedef struct {                                /*!< (@ 0x40012000) DMA Structure                                              */
  __IOM uint32_t  TOP_RST;                      /*!< (@ 0x00000000) TOP_RST Register                                           */
} DMA0_TopRstType;                              /*!< Size = 4 (0x4)                                                            */



/* =========================================================================================================================== */
/* ================                                       DMA_CHANNEL                                         ================ */
/* =========================================================================================================================== */


/**
  * @brief DMA channel (DMA_CHANNEL)
  */

typedef struct {                                /*!< (@ 0x40012040) DMA_CHANNEL Structure                                      */
  __IOM uint32_t  STATUS;                       /*!< (@ 0x00000000) Status Register                                            */
  __IOM uint32_t  INTEN;                        /*!< (@ 0x00000004) Interrupt Enable Register                                  */
  __IOM uint32_t  RST;                          /*!< (@ 0x00000008) Reset Register                                             */
  __IOM uint32_t  STOP;                         /*!< (@ 0x0000000C) Stop Register                                              */
  __IOM uint32_t  CONFIG;                       /*!< (@ 0x00000010) DMA Config Register                                        */
  __IOM uint32_t  CHAN_LENGTH;                  /*!< (@ 0x00000014) Channel Length Register                                    */
  __IOM uint32_t  MEM_START_ADDR;               /*!< (@ 0x00000018) Memory Start Address Register                              */
  __IOM uint32_t  MEM_END_ADDR;                 /*!< (@ 0x0000001C) Memory End Address Register                                */
  __IOM uint32_t  PERIPH_ADDR;                  /*!< (@ 0x00000020) Peripheral Address Register                                */
  __IOM uint32_t  CHAN_ENABLE;                  /*!< (@ 0x00000024) Channel Enable Register                                    */
  __IOM uint32_t  DATA_TRANS_NUM;               /*!< (@ 0x00000028) Data Transfer Number Register                              */
  __IOM uint32_t  FIFO_LEFT_NUM;                /*!< (@ 0x0000002C) Internal FIFO Data Left Number Register                    */
} DMA_ChannelType;                              /*!< Size = 48 (0x30)                                                          */

#define DMA_INSTANCE_MAX              (4UL)     /*!< Number of instances of the DMA Channel                                    */

/* =========================================================================================================================== */
/* ================                                           WDOG                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Watchdog (WDOG)
  */

typedef struct {                                /*!< (@ 0x4000B000) WDG Structure                                             */
  __IOM uint32_t  CS0;                          /*!< (@ 0x00000000) Watchdog Control and Status Register 0                     */
  __IOM uint32_t  CS1;                          /*!< (@ 0x00000004) Watchdog Control and Status Register 1                     */
  __IOM uint32_t  CNT;                          /*!< (@ 0x00000008) Watchdog Counter Value                                     */
  __IOM uint32_t  TOVAL;                        /*!< (@ 0x0000000C) Watchdog Timeout Value Register                            */
  __IOM uint32_t  WIN;                          /*!< (@ 0x00000010) Watchdog Window Register                                   */
} WDG_Type;                                     /*!< Size = 20 (0x14)                                                          */



/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief Real-time counter (RTC)
  */

typedef struct {                                /*!< (@ 0x40008400) RTC Structure                                              */
  __IOM uint32_t  SC;                           /*!< (@ 0x00000000) RTC Status and Control Register                            */
  __IOM uint32_t  MOD;                          /*!< (@ 0x00000004) RTC Modulo Value                                           */
  __IM  uint32_t  CNT;                          /*!< (@ 0x00000008) RTC Count Value                                            */
  __IOM uint32_t  PS;                           /*!< (@ 0x0000000C) RTC Prescaler Register                                     */
  __IM  uint32_t  PSCNT;                        /*!< (@ 0x00000010) RTC Prescaler Counter Register                             */
} RTC_Type;                                     /*!< Size = 20 (0x14)                                                          */



/* =========================================================================================================================== */
/* ================                                         MMDIVSQRT                                         ================ */
/* =========================================================================================================================== */


/**
  * @brief Division and Square root mudule (MMDIVSQRT)
  */

typedef struct {                                /*!< (@ 0x20081800) MMDIVSQRT Structure                                        */
  __IOM uint32_t  DEND;                         /*!< (@ 0x00000000) Dividend Register                                          */
  __IOM uint32_t  DSOR;                         /*!< (@ 0x00000004) Divisor Register                                           */
  __IOM uint32_t  DSFT;                         /*!< (@ 0x00000008) Dividend Shifter Register                                  */
  __IOM uint32_t  RCNDX;                        /*!< (@ 0x0000000C) RCNDX Register                                             */
  __IOM uint32_t  RCNDY;                        /*!< (@ 0x00000010) RCNDY Register                                             */
  __IOM uint32_t  CSR;                          /*!< (@ 0x00000014) Control/Status Register                                    */
  __IM  uint32_t  RESULT;                       /*!< (@ 0x00000018) Result Register                                            */
} MMDIVSQRT_Type;                               /*!< Size = 28 (0x1c)                                                          */



/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief CRC Cyclic redundancy check (CRC)
  */

typedef struct {                                /*!< (@ 0x20081000) CRC Structure                                              */
  union {
      __IOM uint32_t DATA32;                    /*!< (@ 0x00000000) DATA Register                                              */
      struct {
        __IOM uint16_t L;                       /*!< (@ 0x00000000) DATA L Register                                            */
        __IOM uint16_t H;                       /*!< (@ 0x00000002) DATA H Register                                            */
      } DATA16;
      struct {
        __IOM uint8_t LL;                       /*!< (@ 0x00000000) DATA LL Register                                           */
        __IOM uint8_t UL;                       /*!< (@ 0x00000001) DATA UL Register                                           */
        __IOM uint8_t HL;                       /*!< (@ 0x00000002) DATA HL Register                                           */
        __IOM uint8_t HU;                       /*!< (@ 0x00000003) DATA HU Register                                           */
      } DATA8;
  } DATAn;
  __IOM uint32_t  POLY;                         /*!< (@ 0x00000004) POLY Register                                              */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000008) Control Register                                           */
} CRC_Type;                                     /*!< Size = 12 (0xc)                                                           */



/* =========================================================================================================================== */
/* ================                                         ECC_SRAM                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief SRAM Error Check and Correction (ECC_SRAM)
  */

typedef struct {                                /*!< (@ 0x40000020) ECC_SRAM Structure                                         */
  __IOM uint32_t  CTRL;                         /*!< (@ 0x00000000) SRAM ECC status and control register                       */
  __IM  uint32_t  ERR1_ADDR;                    /*!< (@ 0x00000004) ECC 1 bit error address                                    */
  __IM  uint32_t  ERR2_ADDR;                    /*!< (@ 0x00000008) ECC 2 bit error address                                    */
} ECC_SramType;                                 /*!< Size = 12 (0xc)                                                           */

#define ECC_INSTANCE_MAX              (1UL)     /*!< Number of instances of the ECC                                            */    

/* =========================================================================================================================== */
/* ================                                          EFLASH                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Embedded Flash (EFLASH)
  */

typedef struct {                                /*!< (@ 0x40002000) EFLASH Structure                                           */
  __IOM uint32_t  KEY;                          /*!< (@ 0x00000000) Key sequence register                                      */
  __IOM uint32_t  INFO;                         /*!< (@ 0x00000004) Chip information register                                  */
  __IOM uint32_t  ADR_CMD;                      /*!< (@ 0x00000008) Erase start address register                               */
  __IOM uint32_t  CTRL0;                        /*!< (@ 0x0000000C) Control register 0                                         */
  __IOM uint32_t  SR0;                          /*!< (@ 0x00000010) Status register 0                                          */
  __IOM uint32_t  CTRL1;                        /*!< (@ 0x00000014) Control register 1                                         */
  __IOM uint32_t  WPRT_EN0;                     /*!< (@ 0x00000018) Write protect enable register 0                            */
  __IOM uint32_t  WPRT_EN1;                     /*!< (@ 0x0000001C) Write protect enable register 1                            */
  __IM  uint32_t  RESERVED[8];
  __IOM uint32_t  CTRL2;                        /*!< (@ 0x00000040) Control register 2                                         */
} EFLASH_Type;                                  /*!< Size = 68 (0x44)                                                          */


/** @} */ /* End of group Device_Peripheral_peripherals */


/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */

#define CKGEN_BASE                  0x40000000UL
#define SPM_BASE                    0x40008000UL
#define GPIOA_BASE                  0x20080000UL
#define GPIOB_BASE                  0x20080030UL
#define GPIOC_BASE                  0x20080060UL
#define PMUX_BASE                   0x20080140UL
#define EXTI_BASE                   0x20080160UL
#define CAN0_BASE                   0x40007800UL
#define UART0_BASE                  0x40018000UL
#define UART1_BASE                  0x40019000UL
#define UART2_BASE                  0x4001A000UL
#define I2C0_BASE                   0x4000E000UL
#define I2C1_BASE                   0x4000F000UL
#define SPI0_BASE                   0x4000C000UL
#define SPI1_BASE                   0x4000D000UL
#define ADC0_BASE                   0x40003000UL
#define ACMP_ANACFG_BASE            0x40008820UL
#define ACMP0_BASE                  0x40005000UL
#define PWM0_BASE                   0x40013000UL
#define PWM1_BASE                   0x40014000UL
#define PWDT0_BASE                  0x40017000UL
#define PWDT1_BASE                  0x40017800UL
#define TIMER_CTRL_BASE             0x40011000UL
#define TIMER_CHANNEL0_BASE         0x40011100UL
#define TIMER_CHANNEL1_BASE         0x40011110UL
#define TIMER_CHANNEL2_BASE         0x40011120UL
#define TIMER_CHANNEL3_BASE         0x40011130UL
#define CTU_BASE                    0x40016000UL
#define DMA0_TOP_RST_BASE           0x40012000UL
#define DMA0_CHANNEL0_BASE          0x40012040UL
#define DMA0_CHANNEL1_BASE          0x40012080UL
#define DMA0_CHANNEL2_BASE          0x400120C0UL
#define DMA0_CHANNEL3_BASE          0x40012100UL
#define WDG_BASE                    0x4000B000UL
#define RTC_BASE                    0x40008400UL
#define MMDIVSQRT_BASE              0x20081800UL
#define CRC_BASE                    0x20081000UL
#define ECC_SRAM_BASE               0x40000020UL
#define EFLASH_BASE                 0x40002000UL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_declaration
  * @{
  */

#define CKGEN                       ((CKGEN_Type*)             CKGEN_BASE)
#define SPM                         ((SPM_Type*)               SPM_BASE)
#define GPIOA                       ((GPIO_Type*)              GPIOA_BASE)
#define GPIOB                       ((GPIO_Type*)              GPIOB_BASE)
#define GPIOC                       ((GPIO_Type*)              GPIOC_BASE)
#define PMUX                        ((PMUX_Type*)              PMUX_BASE)
#define EXTI                        ((EXTI_Type*)              EXTI_BASE)
#define CAN0                        ((CAN_Type*)               CAN0_BASE)
#define UART0                       ((UART_Type*)              UART0_BASE)
#define UART1                       ((UART_Type*)              UART1_BASE)
#define UART2                       ((UART_Type*)              UART2_BASE)
#define I2C0                        ((I2C_Type*)               I2C0_BASE)
#define I2C1                        ((I2C_Type*)               I2C1_BASE)
#define SPI0                        ((SPI_Type*)               SPI0_BASE)
#define SPI1                        ((SPI_Type*)               SPI1_BASE)
#define ADC0                        ((ADC_Type*)               ADC0_BASE)
#define ACMP_ANACFG                 ((ACMP_ANACfgType*)        ACMP_ANACFG_BASE)
#define ACMP0                       ((ACMP_Type*)              ACMP0_BASE)
#define PWM0                        ((PWM_Type*)               PWM0_BASE)
#define PWM1                        ((PWM_Type*)               PWM1_BASE)
#define PWDT0                       ((PWDT_Type*)              PWDT0_BASE)
#define PWDT1                       ((PWDT_Type*)              PWDT1_BASE)
#define TIMER_CTRL                  ((TIMER_CtrlType*)         TIMER_CTRL_BASE)
#define TIMER_CHANNEL0              ((TIMER_ChannelType*)      TIMER_CHANNEL0_BASE)
#define TIMER_CHANNEL1              ((TIMER_ChannelType*)      TIMER_CHANNEL1_BASE)
#define TIMER_CHANNEL2              ((TIMER_ChannelType*)      TIMER_CHANNEL2_BASE)
#define TIMER_CHANNEL3              ((TIMER_ChannelType*)      TIMER_CHANNEL3_BASE)
#define CTU                         ((CTU_Type*)               CTU_BASE)
#define DMA0_TOP_RST                ((DMA0_TopRstType*)        DMA0_TOP_RST_BASE)
#define DMA0_CHANNEL0               ((DMA_ChannelType*)        DMA0_CHANNEL0_BASE)
#define DMA0_CHANNEL1               ((DMA_ChannelType*)        DMA0_CHANNEL1_BASE)
#define DMA0_CHANNEL2               ((DMA_ChannelType*)        DMA0_CHANNEL2_BASE)
#define DMA0_CHANNEL3               ((DMA_ChannelType*)        DMA0_CHANNEL3_BASE)
#define WDG                         ((WDG_Type*)               WDG_BASE)
#define RTC                         ((RTC_Type*)               RTC_BASE)
#define MMDIVSQRT                   ((MMDIVSQRT_Type*)         MMDIVSQRT_BASE)
#define CRC                         ((CRC_Type*)               CRC_BASE)
#define ECC_SRAM                    ((ECC_SramType*)          ECC_SRAM_BASE)
#define EFLASH                      ((EFLASH_Type*)            EFLASH_BASE)

/** @} */ /* End of group Device_Peripheral_declaration */


/* =========================================================================================================================== */
/* ================                                Pos/Mask Peripheral Section                                ================ */
/* =========================================================================================================================== */


/** @addtogroup PosMask_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                           CKGEN                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define CKGEN_CTRL_SYSCLK_SEL_Pos         (0UL)                     /*!< SYSCLK_SEL (Bit 0)                                    */
#define CKGEN_CTRL_SYSCLK_SEL_Msk         (0x3UL)                   /*!< SYSCLK_SEL (Bitfield-Mask: 0x03)                      */
#define CKGEN_CTRL_SYSCLK_DIV_Pos         (4UL)                     /*!< SYSCLK_DIV (Bit 4)                                    */
#define CKGEN_CTRL_SYSCLK_DIV_Msk         (0x30UL)                  /*!< SYSCLK_DIV (Bitfield-Mask: 0x03)                      */
#define CKGEN_CTRL_APBCLK_DIV_Pos         (8UL)                     /*!< APBCLK_DIV (Bit 8)                                    */
#define CKGEN_CTRL_APBCLK_DIV_Msk         (0x300UL)                 /*!< APBCLK_DIV (Bitfield-Mask: 0x03)                      */
#define CKGEN_CTRL_XOSC_MON_EN_Pos        (16UL)                    /*!< XOSC_MON_EN (Bit 16)                                  */
#define CKGEN_CTRL_XOSC_MON_EN_Msk        (0x10000UL)               /*!< XOSC_MON_EN (Bitfield-Mask: 0x01)                     */
#define CKGEN_CTRL_PLL_REF_SEL_Pos        (20UL)                    /*!< PLL_REF_SEL (Bit 20)                                  */
#define CKGEN_CTRL_PLL_REF_SEL_Msk        (0x100000UL)              /*!< PLL_REF_SEL (Bitfield-Mask: 0x01)                     */
#define CKGEN_CTRL_CAN0_TIMCLK_DIV_Pos    (21UL)                    /*!< CAN0_TIMCLK_DIV (Bit 21)                              */
#define CKGEN_CTRL_CAN0_TIMCLK_DIV_Msk    (0x600000UL)              /*!< CAN0_TIMCLK_DIV (Bitfield-Mask: 0x03)                 */
#define CKGEN_CTRL_CAN0_CLK_SEL_Pos       (26UL)                    /*!< CAN0_CLK_SEL (Bit 26)                                 */
#define CKGEN_CTRL_CAN0_CLK_SEL_Msk       (0x4000000UL)             /*!< CAN0_CLK_SEL (Bitfield-Mask: 0x01)                    */
/* =====================================================  PERI_CLK_EN_0  ===================================================== */
#define CKGEN_PERI_CLK_EN_0_UART0_EN_Pos  (0UL)                     /*!< UART0_EN (Bit 0)                                      */
#define CKGEN_PERI_CLK_EN_0_UART0_EN_Msk  (0x1UL)                   /*!< UART0_EN (Bitfield-Mask: 0x01)                        */
#define CKGEN_PERI_CLK_EN_0_UART1_EN_Pos  (1UL)                     /*!< UART1_EN (Bit 1)                                      */
#define CKGEN_PERI_CLK_EN_0_UART1_EN_Msk  (0x2UL)                   /*!< UART1_EN (Bitfield-Mask: 0x01)                        */
#define CKGEN_PERI_CLK_EN_0_UART2_EN_Pos  (2UL)                     /*!< UART2_EN (Bit 2)                                      */
#define CKGEN_PERI_CLK_EN_0_UART2_EN_Msk  (0x4UL)                   /*!< UART2_EN (Bitfield-Mask: 0x01)                        */
#define CKGEN_PERI_CLK_EN_0_SPI0_EN_Pos   (6UL)                     /*!< SPI0_EN (Bit 6)                                       */
#define CKGEN_PERI_CLK_EN_0_SPI0_EN_Msk   (0x40UL)                  /*!< SPI0_EN (Bitfield-Mask: 0x01)                         */
#define CKGEN_PERI_CLK_EN_0_SPI1_EN_Pos   (7UL)                     /*!< SPI1_EN (Bit 7)                                       */
#define CKGEN_PERI_CLK_EN_0_SPI1_EN_Msk   (0x80UL)                  /*!< SPI1_EN (Bitfield-Mask: 0x01)                         */
#define CKGEN_PERI_CLK_EN_0_I2C0_EN_Pos   (8UL)                     /*!< I2C0_EN (Bit 8)                                       */
#define CKGEN_PERI_CLK_EN_0_I2C0_EN_Msk   (0x100UL)                 /*!< I2C0_EN (Bitfield-Mask: 0x01)                         */
#define CKGEN_PERI_CLK_EN_0_I2C1_EN_Pos   (9UL)                     /*!< I2C1_EN (Bit 9)                                       */
#define CKGEN_PERI_CLK_EN_0_I2C1_EN_Msk   (0x200UL)                 /*!< I2C1_EN (Bitfield-Mask: 0x01)                         */
#define CKGEN_PERI_CLK_EN_0_PWDT0_EN_Pos  (10UL)                    /*!< PWDT0_EN (Bit 10)                                     */
#define CKGEN_PERI_CLK_EN_0_PWDT0_EN_Msk  (0x400UL)                 /*!< PWDT0_EN (Bitfield-Mask: 0x01)                        */
#define CKGEN_PERI_CLK_EN_0_PWM0_EN_Pos   (11UL)                    /*!< PWM0_EN (Bit 11)                                      */
#define CKGEN_PERI_CLK_EN_0_PWM0_EN_Msk   (0x800UL)                 /*!< PWM0_EN (Bitfield-Mask: 0x01)                         */
#define CKGEN_PERI_CLK_EN_0_PWM1_EN_Pos   (12UL)                    /*!< PWM1_EN (Bit 12)                                      */
#define CKGEN_PERI_CLK_EN_0_PWM1_EN_Msk   (0x1000UL)                /*!< PWM1_EN (Bitfield-Mask: 0x01)                         */
#define CKGEN_PERI_CLK_EN_0_TIMER_EN_Pos  (19UL)                    /*!< TIMER_EN (Bit 19)                                     */
#define CKGEN_PERI_CLK_EN_0_TIMER_EN_Msk  (0x80000UL)               /*!< TIMER_EN (Bitfield-Mask: 0x01)                        */
#define CKGEN_PERI_CLK_EN_0_RTC_EN_Pos    (20UL)                    /*!< RTC_EN (Bit 20)                                       */
#define CKGEN_PERI_CLK_EN_0_RTC_EN_Msk    (0x100000UL)              /*!< RTC_EN (Bitfield-Mask: 0x01)                          */
#define CKGEN_PERI_CLK_EN_0_DMA0_EN_Pos   (21UL)                    /*!< DMA0_EN (Bit 21)                                      */
#define CKGEN_PERI_CLK_EN_0_DMA0_EN_Msk   (0x200000UL)              /*!< DMA0_EN (Bitfield-Mask: 0x01)                         */
#define CKGEN_PERI_CLK_EN_0_GPIO_EN_Pos   (23UL)                    /*!< GPIO_EN (Bit 23)                                      */
#define CKGEN_PERI_CLK_EN_0_GPIO_EN_Msk   (0x800000UL)              /*!< GPIO_EN (Bitfield-Mask: 0x01)                         */
#define CKGEN_PERI_CLK_EN_0_WDG_EN_Pos    (25UL)                    /*!< WDG_EN (Bit 25)                                       */
#define CKGEN_PERI_CLK_EN_0_WDG_EN_Msk    (0x2000000UL)             /*!< WDG_EN (Bitfield-Mask: 0x01)                          */
#define CKGEN_PERI_CLK_EN_0_CRC_EN_Pos    (26UL)                    /*!< CRC_EN (Bit 26)                                       */
#define CKGEN_PERI_CLK_EN_0_CRC_EN_Msk    (0x4000000UL)             /*!< CRC_EN (Bitfield-Mask: 0x01)                          */
#define CKGEN_PERI_CLK_EN_0_CAN0_EN_Pos   (28UL)                    /*!< CAN0_EN (Bit 28)                                      */
#define CKGEN_PERI_CLK_EN_0_CAN0_EN_Msk   (0x10000000UL)            /*!< CAN0_EN (Bitfield-Mask: 0x01)                         */
/* =====================================================  PERI_CLK_EN_1  ===================================================== */
#define CKGEN_PERI_CLK_EN_1_CTU_EN_Pos    (1UL)                     /*!< CTU_EN (Bit 1)                                        */
#define CKGEN_PERI_CLK_EN_1_CTU_EN_Msk    (0x2UL)                   /*!< CTU_EN (Bitfield-Mask: 0x01)                          */
#define CKGEN_PERI_CLK_EN_1_ADC0_EN_Pos   (2UL)                     /*!< ADC0_EN (Bit 2)                                       */
#define CKGEN_PERI_CLK_EN_1_ADC0_EN_Msk   (0x4UL)                   /*!< ADC0_EN (Bitfield-Mask: 0x01)                         */
#define CKGEN_PERI_CLK_EN_1_ACMP0_EN_Pos  (3UL)                     /*!< ACMP0_EN (Bit 3)                                      */
#define CKGEN_PERI_CLK_EN_1_ACMP0_EN_Msk  (0x8UL)                   /*!< ACMP0_EN (Bitfield-Mask: 0x01)                        */
#define CKGEN_PERI_CLK_EN_1_PWDT1_EN_Pos  (5UL)                     /*!< PWDT1_EN (Bit 5)                                      */
#define CKGEN_PERI_CLK_EN_1_PWDT1_EN_Msk  (0x20UL)                  /*!< PWDT1_EN (Bitfield-Mask: 0x01)                        */
/* ======================================================  RESET_CTRL  ======================================================= */
#define CKGEN_RESET_CTRL_EXT_RST_DEGLITCH_EN_Pos (0UL)              /*!< EXT_RST_DEGLITCH_EN (Bit 0)                           */
#define CKGEN_RESET_CTRL_EXT_RST_DEGLITCH_EN_Msk (0x1UL)            /*!< EXT_RST_DEGLITCH_EN (Bitfield-Mask: 0x01)             */
#define CKGEN_RESET_CTRL_EXT_RST_DEGLITCH_VALUE_Pos (1UL)           /*!< EXT_RST_DEGLITCH_VALUE (Bit 1)                        */
#define CKGEN_RESET_CTRL_EXT_RST_DEGLITCH_VALUE_Msk (0xfeUL)        /*!< EXT_RST_DEGLITCH_VALUE (Bitfield-Mask: 0x7f)          */
#define CKGEN_RESET_CTRL_PLL_UNLOCK_RST_EN_Pos (22UL)               /*!< PLL_UNLOCK_RST_EN (Bit 22)                            */
#define CKGEN_RESET_CTRL_PLL_UNLOCK_RST_EN_Msk (0x400000UL)         /*!< PLL_UNLOCK_RST_EN (Bitfield-Mask: 0x01)               */
#define CKGEN_RESET_CTRL_ECC2_RST_EN_Pos  (23UL)                    /*!< ECC2_RST_EN (Bit 23)                                  */
#define CKGEN_RESET_CTRL_ECC2_RST_EN_Msk  (0x800000UL)              /*!< ECC2_RST_EN (Bitfield-Mask: 0x01)                     */
#define CKGEN_RESET_CTRL_CPU_SYSRST_EN_Pos (24UL)                   /*!< CPU_SYSRST_EN (Bit 24)                                */
#define CKGEN_RESET_CTRL_CPU_SYSRST_EN_Msk (0x1000000UL)            /*!< CPU_SYSRST_EN (Bitfield-Mask: 0x01)                   */
#define CKGEN_RESET_CTRL_CPU_LOCKUP_RST_EN_Pos (25UL)               /*!< CPU_LOCKUP_RST_EN (Bit 25)                            */
#define CKGEN_RESET_CTRL_CPU_LOCKUP_RST_EN_Msk (0x2000000UL)        /*!< CPU_LOCKUP_RST_EN (Bitfield-Mask: 0x01)               */
#define CKGEN_RESET_CTRL_XOSC_LOSS_RST_EN_Pos (26UL)                /*!< XOSC_LOSS_RST_EN (Bit 26)                             */
#define CKGEN_RESET_CTRL_XOSC_LOSS_RST_EN_Msk (0x4000000UL)         /*!< XOSC_LOSS_RST_EN (Bitfield-Mask: 0x01)                */
/* =====================================================  RESET_STATUS  ====================================================== */
#define CKGEN_RESET_STATUS_POR_RESET_STATUS_Pos (0UL)               /*!< POR_RESET_STATUS (Bit 0)                              */
#define CKGEN_RESET_STATUS_POR_RESET_STATUS_Msk (0x1UL)             /*!< POR_RESET_STATUS (Bitfield-Mask: 0x01)                */
#define CKGEN_RESET_STATUS_LVD_RESET_STATUS_Pos (1UL)               /*!< LVD_RESET_STATUS (Bit 1)                              */
#define CKGEN_RESET_STATUS_LVD_RESET_STATUS_Msk (0x2UL)             /*!< LVD_RESET_STATUS (Bitfield-Mask: 0x01)                */
#define CKGEN_RESET_STATUS_EXT_RESET_STATUS_Pos (2UL)               /*!< EXT_RESET_STATUS (Bit 2)                              */
#define CKGEN_RESET_STATUS_EXT_RESET_STATUS_Msk (0x4UL)             /*!< EXT_RESET_STATUS (Bitfield-Mask: 0x01)                */
#define CKGEN_RESET_STATUS_WDT_RESET_STATUS_Pos (4UL)               /*!< WDT_RESET_STATUS (Bit 4)                              */
#define CKGEN_RESET_STATUS_WDT_RESET_STATUS_Msk (0x10UL)            /*!< WDT_RESET_STATUS (Bitfield-Mask: 0x01)                */
#define CKGEN_RESET_STATUS_WDT_32K_RESET_STATUS_Pos (5UL)           /*!< WDT_32K_RESET_STATUS (Bit 5)                          */
#define CKGEN_RESET_STATUS_WDT_32K_RESET_STATUS_Msk (0x20UL)        /*!< WDT_32K_RESET_STATUS (Bitfield-Mask: 0x01)            */
#define CKGEN_RESET_STATUS_CPU_SYSRESET_STATUS_Pos (6UL)            /*!< CPU_SYSRESET_STATUS (Bit 6)                           */
#define CKGEN_RESET_STATUS_CPU_SYSRESET_STATUS_Msk (0x40UL)         /*!< CPU_SYSRESET_STATUS (Bitfield-Mask: 0x01)             */
#define CKGEN_RESET_STATUS_CPU_LOCKUP_RST_STATUS_Pos (7UL)          /*!< CPU_LOCKUP_RST_STATUS (Bit 7)                         */
#define CKGEN_RESET_STATUS_CPU_LOCKUP_RST_STATUS_Msk (0x80UL)       /*!< CPU_LOCKUP_RST_STATUS (Bitfield-Mask: 0x01)           */
#define CKGEN_RESET_STATUS_PLL_UNLOCK_RST_STATUS_Pos (8UL)          /*!< PLL_UNLOCK_RST_STATUS (Bit 8)                         */
#define CKGEN_RESET_STATUS_PLL_UNLOCK_RST_STATUS_Msk (0x100UL)      /*!< PLL_UNLOCK_RST_STATUS (Bitfield-Mask: 0x01)           */
#define CKGEN_RESET_STATUS_XOSC_LOSS_STATUS_Pos (9UL)               /*!< XOSC_LOSS_STATUS (Bit 9)                              */
#define CKGEN_RESET_STATUS_XOSC_LOSS_STATUS_Msk (0x200UL)           /*!< XOSC_LOSS_STATUS (Bitfield-Mask: 0x01)                */
#define CKGEN_RESET_STATUS_CLR_RESET_STATUS_Pos (16UL)              /*!< CLR_RESET_STATUS (Bit 16)                             */
#define CKGEN_RESET_STATUS_CLR_RESET_STATUS_Msk (0x10000UL)         /*!< CLR_RESET_STATUS (Bitfield-Mask: 0x01)                */
/* =====================================================  PERI_SFT_RST0  ===================================================== */
#define CKGEN_PERI_SFT_RST0_SRST_UART0_Pos (0UL)                    /*!< SRST_UART0 (Bit 0)                                    */
#define CKGEN_PERI_SFT_RST0_SRST_UART0_Msk (0x1UL)                  /*!< SRST_UART0 (Bitfield-Mask: 0x01)                      */
#define CKGEN_PERI_SFT_RST0_SRST_UART1_Pos (1UL)                    /*!< SRST_UART1 (Bit 1)                                    */
#define CKGEN_PERI_SFT_RST0_SRST_UART1_Msk (0x2UL)                  /*!< SRST_UART1 (Bitfield-Mask: 0x01)                      */
#define CKGEN_PERI_SFT_RST0_SRST_UART2_Pos (2UL)                    /*!< SRST_UART2 (Bit 2)                                    */
#define CKGEN_PERI_SFT_RST0_SRST_UART2_Msk (0x4UL)                  /*!< SRST_UART2 (Bitfield-Mask: 0x01)                      */
#define CKGEN_PERI_SFT_RST0_SRST_SPI0_Pos (6UL)                     /*!< SRST_SPI0 (Bit 6)                                     */
#define CKGEN_PERI_SFT_RST0_SRST_SPI0_Msk (0x40UL)                  /*!< SRST_SPI0 (Bitfield-Mask: 0x01)                       */
#define CKGEN_PERI_SFT_RST0_SRST_SPI1_Pos (7UL)                     /*!< SRST_SPI1 (Bit 7)                                     */
#define CKGEN_PERI_SFT_RST0_SRST_SPI1_Msk (0x80UL)                  /*!< SRST_SPI1 (Bitfield-Mask: 0x01)                       */
#define CKGEN_PERI_SFT_RST0_SRST_I2C0_Pos (8UL)                     /*!< SRST_I2C0 (Bit 8)                                     */
#define CKGEN_PERI_SFT_RST0_SRST_I2C0_Msk (0x100UL)                 /*!< SRST_I2C0 (Bitfield-Mask: 0x01)                       */
#define CKGEN_PERI_SFT_RST0_SRST_I2C1_Pos (9UL)                     /*!< SRST_I2C1 (Bit 9)                                     */
#define CKGEN_PERI_SFT_RST0_SRST_I2C1_Msk (0x200UL)                 /*!< SRST_I2C1 (Bitfield-Mask: 0x01)                       */
#define CKGEN_PERI_SFT_RST0_SRST_PWDT0_Pos (10UL)                   /*!< SRST_PWDT0 (Bit 10)                                   */
#define CKGEN_PERI_SFT_RST0_SRST_PWDT0_Msk (0x400UL)                /*!< SRST_PWDT0 (Bitfield-Mask: 0x01)                      */
#define CKGEN_PERI_SFT_RST0_SRST_PWM0_Pos (11UL)                    /*!< SRST_PWM0 (Bit 11)                                    */
#define CKGEN_PERI_SFT_RST0_SRST_PWM0_Msk (0x800UL)                 /*!< SRST_PWM0 (Bitfield-Mask: 0x01)                       */
#define CKGEN_PERI_SFT_RST0_SRST_PWM1_Pos (12UL)                    /*!< SRST_PWM1 (Bit 12)                                    */
#define CKGEN_PERI_SFT_RST0_SRST_PWM1_Msk (0x1000UL)                /*!< SRST_PWM1 (Bitfield-Mask: 0x01)                       */
#define CKGEN_PERI_SFT_RST0_SRST_TIMER_Pos (19UL)                   /*!< SRST_TIMER (Bit 19)                                   */
#define CKGEN_PERI_SFT_RST0_SRST_TIMER_Msk (0x80000UL)              /*!< SRST_TIMER (Bitfield-Mask: 0x01)                      */
#define CKGEN_PERI_SFT_RST0_SRST_RTC_Pos  (20UL)                    /*!< SRST_RTC (Bit 20)                                     */
#define CKGEN_PERI_SFT_RST0_SRST_RTC_Msk  (0x100000UL)              /*!< SRST_RTC (Bitfield-Mask: 0x01)                        */
#define CKGEN_PERI_SFT_RST0_SRST_DMA0_Pos (21UL)                    /*!< SRST_DMA0 (Bit 21)                                    */
#define CKGEN_PERI_SFT_RST0_SRST_DMA0_Msk (0x200000UL)              /*!< SRST_DMA0 (Bitfield-Mask: 0x01)                       */
#define CKGEN_PERI_SFT_RST0_SRST_GPIO_Pos (23UL)                    /*!< SRST_GPIO (Bit 23)                                    */
#define CKGEN_PERI_SFT_RST0_SRST_GPIO_Msk (0x800000UL)              /*!< SRST_GPIO (Bitfield-Mask: 0x01)                       */
#define CKGEN_PERI_SFT_RST0_SRST_WDG_Pos  (25UL)                    /*!< SRST_WDG (Bit 25)                                     */
#define CKGEN_PERI_SFT_RST0_SRST_WDG_Msk  (0x2000000UL)             /*!< SRST_WDG (Bitfield-Mask: 0x01)                        */
#define CKGEN_PERI_SFT_RST0_SRST_CRC_Pos  (26UL)                    /*!< SRST_CRC (Bit 26)                                     */
#define CKGEN_PERI_SFT_RST0_SRST_CRC_Msk  (0x4000000UL)             /*!< SRST_CRC (Bitfield-Mask: 0x01)                        */
#define CKGEN_PERI_SFT_RST0_SRST_CAN0_Pos (28UL)                    /*!< SRST_CAN0 (Bit 28)                                    */
#define CKGEN_PERI_SFT_RST0_SRST_CAN0_Msk (0x10000000UL)            /*!< SRST_CAN0 (Bitfield-Mask: 0x01)                       */
/* =====================================================  PERI_SFT_RST1  ===================================================== */
#define CKGEN_PERI_SFT_RST1_SRST_CTU_Pos  (1UL)                     /*!< SRST_CTU (Bit 1)                                      */
#define CKGEN_PERI_SFT_RST1_SRST_CTU_Msk  (0x2UL)                   /*!< SRST_CTU (Bitfield-Mask: 0x01)                        */
#define CKGEN_PERI_SFT_RST1_SRST_ADC0_Pos (2UL)                     /*!< SRST_ADC0 (Bit 2)                                     */
#define CKGEN_PERI_SFT_RST1_SRST_ADC0_Msk (0x4UL)                   /*!< SRST_ADC0 (Bitfield-Mask: 0x01)                       */
#define CKGEN_PERI_SFT_RST1_SRST_ACMP0_Pos (3UL)                    /*!< SRST_ACMP0 (Bit 3)                                    */
#define CKGEN_PERI_SFT_RST1_SRST_ACMP0_Msk (0x8UL)                  /*!< SRST_ACMP0 (Bitfield-Mask: 0x01)                      */
#define CKGEN_PERI_SFT_RST1_SRST_ANA_REG_Pos (4UL)                  /*!< SRST_ANA_REG (Bit 4)                                  */
#define CKGEN_PERI_SFT_RST1_SRST_ANA_REG_Msk (0x10UL)               /*!< SRST_ANA_REG (Bitfield-Mask: 0x01)                    */
#define CKGEN_PERI_SFT_RST1_SRST_PWDT1_Pos (5UL)                    /*!< SRST_PWDT1 (Bit 5)                                    */
#define CKGEN_PERI_SFT_RST1_SRST_PWDT1_Msk (0x20UL)                 /*!< SRST_PWDT1 (Bitfield-Mask: 0x01)                      */
/* =====================================================  SYSPLL1_CFG0  ====================================================== */
#define CKGEN_SYSPLL1_CFG0_SYSPLL1_FBKDIV_Pos (15UL)                /*!< SYSPLL1_FBKDIV (Bit 15)                               */
#define CKGEN_SYSPLL1_CFG0_SYSPLL1_FBKDIV_Msk (0x7f8000UL)          /*!< SYSPLL1_FBKDIV (Bitfield-Mask: 0xff)                  */
#define CKGEN_SYSPLL1_CFG0_SYSPLL1_POSDIV_Pos (25UL)                /*!< SYSPLL1_POSDIV (Bit 25)                               */
#define CKGEN_SYSPLL1_CFG0_SYSPLL1_POSDIV_Msk (0x3e000000UL)        /*!< SYSPLL1_POSDIV (Bitfield-Mask: 0x1f)                  */
#define CKGEN_SYSPLL1_CFG0_SYSPLL1_PREDIV_Pos (30UL)                /*!< SYSPLL1_PREDIV (Bit 30)                               */
#define CKGEN_SYSPLL1_CFG0_SYSPLL1_PREDIV_Msk (0xc0000000UL)        /*!< SYSPLL1_PREDIV (Bitfield-Mask: 0x03)                  */


/* =========================================================================================================================== */
/* ================                                            SPM                                            ================ */
/* =========================================================================================================================== */

/* =====================================================  PWR_MGR_CFG0  ====================================================== */
#define SPM_PWR_MGR_CFG0_PWR_EN_Pos       (0UL)                     /*!< PWR_EN (Bit 0)                                        */
#define SPM_PWR_MGR_CFG0_PWR_EN_Msk       (0x1UL)                   /*!< PWR_EN (Bitfield-Mask: 0x01)                          */
#define SPM_PWR_MGR_CFG0_EN_FAST_BOOT_Pos (1UL)                     /*!< EN_FAST_BOOT (Bit 1)                                  */
#define SPM_PWR_MGR_CFG0_EN_FAST_BOOT_Msk (0x2UL)                   /*!< EN_FAST_BOOT (Bitfield-Mask: 0x01)                    */
#define SPM_PWR_MGR_CFG0_EN_PVD_Pos       (2UL)                     /*!< EN_PVD (Bit 2)                                        */
#define SPM_PWR_MGR_CFG0_EN_PVD_Msk       (0x4UL)                   /*!< EN_PVD (Bitfield-Mask: 0x01)                          */
#define SPM_PWR_MGR_CFG0_EN_DPWRLVD_Pos   (3UL)                     /*!< EN_DPWRLVD (Bit 3)                                    */
#define SPM_PWR_MGR_CFG0_EN_DPWRLVD_Msk   (0x8UL)                   /*!< EN_DPWRLVD (Bitfield-Mask: 0x01)                      */
#define SPM_PWR_MGR_CFG0_EN_LVD_Pos       (4UL)                     /*!< EN_LVD (Bit 4)                                        */
#define SPM_PWR_MGR_CFG0_EN_LVD_Msk       (0x10UL)                  /*!< EN_LVD (Bitfield-Mask: 0x01)                          */
#define SPM_PWR_MGR_CFG0_EN_CAN0_FILTER_Pos (5UL)                   /*!< EN_CAN0_FILTER (Bit 5)                                */
#define SPM_PWR_MGR_CFG0_EN_CAN0_FILTER_Msk (0x20UL)                /*!< EN_CAN0_FILTER (Bitfield-Mask: 0x01)                  */
#define SPM_PWR_MGR_CFG0_EN_IO_SUS_Pos    (7UL)                     /*!< EN_IO_SUS (Bit 7)                                     */
#define SPM_PWR_MGR_CFG0_EN_IO_SUS_Msk    (0x80UL)                  /*!< EN_IO_SUS (Bitfield-Mask: 0x01)                       */
#define SPM_PWR_MGR_CFG0_SLEEP_MODE_Pos   (8UL)                     /*!< SLEEP_MODE (Bit 8)                                    */
#define SPM_PWR_MGR_CFG0_SLEEP_MODE_Msk   (0x300UL)                 /*!< SLEEP_MODE (Bitfield-Mask: 0x03)                      */
/* =====================================================  PWR_MGR_CFG1  ====================================================== */
#define SPM_PWR_MGR_CFG1_PORLPVD_Pos      (0UL)                     /*!< PORLPVD (Bit 0)                                       */
#define SPM_PWR_MGR_CFG1_PORLPVD_Msk      (0xfUL)                   /*!< PORLPVD (Bitfield-Mask: 0x0f)                         */
#define SPM_PWR_MGR_CFG1_SYSPLL_ON_Pos    (27UL)                    /*!< SYSPLL_ON (Bit 27)                                    */
#define SPM_PWR_MGR_CFG1_SYSPLL_ON_Msk    (0x8000000UL)             /*!< SYSPLL_ON (Bitfield-Mask: 0x01)                       */
#define SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Pos  (28UL)                    /*!< XOSC_HSEBYP (Bit 28)                                  */
#define SPM_PWR_MGR_CFG1_XOSC_HSEBYP_Msk  (0x10000000UL)            /*!< XOSC_HSEBYP (Bitfield-Mask: 0x01)                     */
#define SPM_PWR_MGR_CFG1_XOSC_HSEON_Pos   (29UL)                    /*!< XOSC_HSEON (Bit 29)                                   */
#define SPM_PWR_MGR_CFG1_XOSC_HSEON_Msk   (0x20000000UL)            /*!< XOSC_HSEON (Bitfield-Mask: 0x01)                      */
#define SPM_PWR_MGR_CFG1_SYSPLL_RDY_Pos   (30UL)                    /*!< SYSPLL_RDY (Bit 30)                                   */
#define SPM_PWR_MGR_CFG1_SYSPLL_RDY_Msk   (0x40000000UL)            /*!< SYSPLL_RDY (Bitfield-Mask: 0x01)                      */
#define SPM_PWR_MGR_CFG1_XOSC_RDY_Pos     (31UL)                    /*!< XOSC_RDY (Bit 31)                                     */
#define SPM_PWR_MGR_CFG1_XOSC_RDY_Msk     (0x80000000UL)            /*!< XOSC_RDY (Bitfield-Mask: 0x01)                        */
/* ================================================  PERIPH_SLEEP_ACK_STATUS  ================================================ */
#define SPM_PERIPH_SLEEP_ACK_STATUS_ACMP0_Pos (0UL)                 /*!< ACMP0 (Bit 0)                                         */
#define SPM_PERIPH_SLEEP_ACK_STATUS_ACMP0_Msk (0x1UL)               /*!< ACMP0 (Bitfield-Mask: 0x01)                           */
#define SPM_PERIPH_SLEEP_ACK_STATUS_I2C0_Pos (2UL)                  /*!< I2C0 (Bit 2)                                          */
#define SPM_PERIPH_SLEEP_ACK_STATUS_I2C0_Msk (0x4UL)                /*!< I2C0 (Bitfield-Mask: 0x01)                            */
#define SPM_PERIPH_SLEEP_ACK_STATUS_I2C1_Pos (3UL)                  /*!< I2C1 (Bit 3)                                          */
#define SPM_PERIPH_SLEEP_ACK_STATUS_I2C1_Msk (0x8UL)                /*!< I2C1 (Bitfield-Mask: 0x01)                            */
#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI0_Pos (4UL)                  /*!< SPI0 (Bit 4)                                          */
#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI0_Msk (0x10UL)               /*!< SPI0 (Bitfield-Mask: 0x01)                            */
#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI1_Pos (5UL)                  /*!< SPI1 (Bit 5)                                          */
#define SPM_PERIPH_SLEEP_ACK_STATUS_SPI1_Msk (0x20UL)               /*!< SPI1 (Bitfield-Mask: 0x01)                            */
#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN0_Pos (7UL)                  /*!< CAN0 (Bit 7)                                          */
#define SPM_PERIPH_SLEEP_ACK_STATUS_CAN0_Msk (0x80UL)               /*!< CAN0 (Bitfield-Mask: 0x01)                            */
#define SPM_PERIPH_SLEEP_ACK_STATUS_UART0_Pos (9UL)                 /*!< UART0 (Bit 9)                                         */
#define SPM_PERIPH_SLEEP_ACK_STATUS_UART0_Msk (0x200UL)             /*!< UART0 (Bitfield-Mask: 0x01)                           */
#define SPM_PERIPH_SLEEP_ACK_STATUS_UART1_Pos (10UL)                /*!< UART1 (Bit 10)                                        */
#define SPM_PERIPH_SLEEP_ACK_STATUS_UART1_Msk (0x400UL)             /*!< UART1 (Bitfield-Mask: 0x01)                           */
#define SPM_PERIPH_SLEEP_ACK_STATUS_UART2_Pos (11UL)                /*!< UART2 (Bit 11)                                        */
#define SPM_PERIPH_SLEEP_ACK_STATUS_UART2_Msk (0x800UL)             /*!< UART2 (Bitfield-Mask: 0x01)                           */
#define SPM_PERIPH_SLEEP_ACK_STATUS_DMA0_Pos (15UL)                 /*!< DMA0 (Bit 15)                                         */
#define SPM_PERIPH_SLEEP_ACK_STATUS_DMA0_Msk (0x8000UL)             /*!< DMA0 (Bitfield-Mask: 0x01)                            */
#define SPM_PERIPH_SLEEP_ACK_STATUS_ADC0_Pos (16UL)                 /*!< ADC0 (Bit 16)                                         */
#define SPM_PERIPH_SLEEP_ACK_STATUS_ADC0_Msk (0x10000UL)            /*!< ADC0 (Bitfield-Mask: 0x01)                            */
#define SPM_PERIPH_SLEEP_ACK_STATUS_EFLASH_Pos (18UL)               /*!< EFLASH (Bit 18)                                       */
#define SPM_PERIPH_SLEEP_ACK_STATUS_EFLASH_Msk (0x40000UL)          /*!< EFLASH (Bitfield-Mask: 0x01)                          */
/* ==================================================  EN_PERIPH_SLEEP_ACK  ================================================== */
#define SPM_EN_PERIPH_SLEEP_ACK_ACMP0_Pos (0UL)                     /*!< ACMP0 (Bit 0)                                         */
#define SPM_EN_PERIPH_SLEEP_ACK_ACMP0_Msk (0x1UL)                   /*!< ACMP0 (Bitfield-Mask: 0x01)                           */
#define SPM_EN_PERIPH_SLEEP_ACK_I2C0_Pos  (2UL)                     /*!< I2C0 (Bit 2)                                          */
#define SPM_EN_PERIPH_SLEEP_ACK_I2C0_Msk  (0x4UL)                   /*!< I2C0 (Bitfield-Mask: 0x01)                            */
#define SPM_EN_PERIPH_SLEEP_ACK_I2C1_Pos  (3UL)                     /*!< I2C1 (Bit 3)                                          */
#define SPM_EN_PERIPH_SLEEP_ACK_I2C1_Msk  (0x8UL)                   /*!< I2C1 (Bitfield-Mask: 0x01)                            */
#define SPM_EN_PERIPH_SLEEP_ACK_SPI0_Pos  (4UL)                     /*!< SPI0 (Bit 4)                                          */
#define SPM_EN_PERIPH_SLEEP_ACK_SPI0_Msk  (0x10UL)                  /*!< SPI0 (Bitfield-Mask: 0x01)                            */
#define SPM_EN_PERIPH_SLEEP_ACK_SPI1_Pos  (5UL)                     /*!< SPI1 (Bit 5)                                          */
#define SPM_EN_PERIPH_SLEEP_ACK_SPI1_Msk  (0x20UL)                  /*!< SPI1 (Bitfield-Mask: 0x01)                            */
#define SPM_EN_PERIPH_SLEEP_ACK_CAN0_Pos  (7UL)                     /*!< CAN0 (Bit 7)                                          */
#define SPM_EN_PERIPH_SLEEP_ACK_CAN0_Msk  (0x80UL)                  /*!< CAN0 (Bitfield-Mask: 0x01)                            */
#define SPM_EN_PERIPH_SLEEP_ACK_UART0_Pos (9UL)                     /*!< UART0 (Bit 9)                                         */
#define SPM_EN_PERIPH_SLEEP_ACK_UART0_Msk (0x200UL)                 /*!< UART0 (Bitfield-Mask: 0x01)                           */
#define SPM_EN_PERIPH_SLEEP_ACK_UART1_Pos (10UL)                    /*!< UART1 (Bit 10)                                        */
#define SPM_EN_PERIPH_SLEEP_ACK_UART1_Msk (0x400UL)                 /*!< UART1 (Bitfield-Mask: 0x01)                           */
#define SPM_EN_PERIPH_SLEEP_ACK_UART2_Pos (11UL)                    /*!< UART2 (Bit 11)                                        */
#define SPM_EN_PERIPH_SLEEP_ACK_UART2_Msk (0x800UL)                 /*!< UART2 (Bitfield-Mask: 0x01)                           */
#define SPM_EN_PERIPH_SLEEP_ACK_DMA0_Pos  (15UL)                    /*!< DMA0 (Bit 15)                                         */
#define SPM_EN_PERIPH_SLEEP_ACK_DMA0_Msk  (0x8000UL)                /*!< DMA0 (Bitfield-Mask: 0x01)                            */
#define SPM_EN_PERIPH_SLEEP_ACK_ADC0_Pos  (16UL)                    /*!< ADC0 (Bit 16)                                         */
#define SPM_EN_PERIPH_SLEEP_ACK_ADC0_Msk  (0x10000UL)               /*!< ADC0 (Bitfield-Mask: 0x01)                            */
#define SPM_EN_PERIPH_SLEEP_ACK_EFLASH_Pos (18UL)                   /*!< EFLASH (Bit 18)                                       */
#define SPM_EN_PERIPH_SLEEP_ACK_EFLASH_Msk (0x40000UL)              /*!< EFLASH (Bitfield-Mask: 0x01)                          */
/* ===================================================  EN_PERIPH_WAKEUP  ==================================================== */
#define SPM_EN_PERIPH_WAKEUP_ACMP0_Pos    (0UL)                     /*!< ACMP0 (Bit 0)                                         */
#define SPM_EN_PERIPH_WAKEUP_ACMP0_Msk    (0x1UL)                   /*!< ACMP0 (Bitfield-Mask: 0x01)                           */
#define SPM_EN_PERIPH_WAKEUP_I2C0_Pos     (2UL)                     /*!< I2C0 (Bit 2)                                          */
#define SPM_EN_PERIPH_WAKEUP_I2C0_Msk     (0x4UL)                   /*!< I2C0 (Bitfield-Mask: 0x01)                            */
#define SPM_EN_PERIPH_WAKEUP_I2C1_Pos     (3UL)                     /*!< I2C1 (Bit 3)                                          */
#define SPM_EN_PERIPH_WAKEUP_I2C1_Msk     (0x8UL)                   /*!< I2C1 (Bitfield-Mask: 0x01)                            */
#define SPM_EN_PERIPH_WAKEUP_SPI0_Pos     (4UL)                     /*!< SPI0 (Bit 4)                                          */
#define SPM_EN_PERIPH_WAKEUP_SPI0_Msk     (0x10UL)                  /*!< SPI0 (Bitfield-Mask: 0x01)                            */
#define SPM_EN_PERIPH_WAKEUP_SPI1_Pos     (5UL)                     /*!< SPI1 (Bit 5)                                          */
#define SPM_EN_PERIPH_WAKEUP_SPI1_Msk     (0x20UL)                  /*!< SPI1 (Bitfield-Mask: 0x01)                            */
#define SPM_EN_PERIPH_WAKEUP_CAN0_Pos     (7UL)                     /*!< CAN0 (Bit 7)                                          */
#define SPM_EN_PERIPH_WAKEUP_CAN0_Msk     (0x80UL)                  /*!< CAN0 (Bitfield-Mask: 0x01)                            */
#define SPM_EN_PERIPH_WAKEUP_UART0_Pos    (9UL)                     /*!< UART0 (Bit 9)                                         */
#define SPM_EN_PERIPH_WAKEUP_UART0_Msk    (0x200UL)                 /*!< UART0 (Bitfield-Mask: 0x01)                           */
#define SPM_EN_PERIPH_WAKEUP_UART1_Pos    (10UL)                    /*!< UART1 (Bit 10)                                        */
#define SPM_EN_PERIPH_WAKEUP_UART1_Msk    (0x400UL)                 /*!< UART1 (Bitfield-Mask: 0x01)                           */
#define SPM_EN_PERIPH_WAKEUP_UART2_Pos    (11UL)                    /*!< UART2 (Bit 11)                                        */
#define SPM_EN_PERIPH_WAKEUP_UART2_Msk    (0x800UL)                 /*!< UART2 (Bitfield-Mask: 0x01)                           */
#define SPM_EN_PERIPH_WAKEUP_RTC_Pos      (15UL)                    /*!< RTC (Bit 15)                                         */
#define SPM_EN_PERIPH_WAKEUP_RTC_Msk      (0x8000UL)                /*!< RTC (Bitfield-Mask: 0x01)                            */
#define SPM_EN_PERIPH_WAKEUP_ADC0_Pos     (16UL)                    /*!< ADC0 (Bit 16)                                         */
#define SPM_EN_PERIPH_WAKEUP_ADC0_Msk     (0x10000UL)               /*!< ADC0 (Bitfield-Mask: 0x01)                            */
#define SPM_EN_PERIPH_WAKEUP_GPIO_Pos     (17UL)                    /*!< GPIO (Bit 17)                                         */
#define SPM_EN_PERIPH_WAKEUP_GPIO_Msk     (0x20000UL)               /*!< GPIO (Bitfield-Mask: 0x01)                            */
#define SPM_EN_PERIPH_WAKEUP_NMI_Pos      (18UL)                    /*!< NMI (Bit 18)                                          */
#define SPM_EN_PERIPH_WAKEUP_NMI_Msk      (0x40000UL)               /*!< NMI (Bitfield-Mask: 0x01)                             */
#define SPM_EN_PERIPH_WAKEUP_PVD_Pos      (19UL)                    /*!< PVD (Bit 19)                                          */
#define SPM_EN_PERIPH_WAKEUP_PVD_Msk      (0x80000UL)               /*!< PVD (Bitfield-Mask: 0x01)                             */
/* ===================================================  WAKEUP_IRQ_STATUS  =================================================== */
#define SPM_WAKEUP_IRQ_STATUS_ACMP0_Pos   (0UL)                     /*!< ACMP0 (Bit 0)                                         */
#define SPM_WAKEUP_IRQ_STATUS_ACMP0_Msk   (0x1UL)                   /*!< ACMP0 (Bitfield-Mask: 0x01)                           */
#define SPM_WAKEUP_IRQ_STATUS_I2C0_Pos    (2UL)                     /*!< I2C0 (Bit 2)                                          */
#define SPM_WAKEUP_IRQ_STATUS_I2C0_Msk    (0x4UL)                   /*!< I2C0 (Bitfield-Mask: 0x01)                            */
#define SPM_WAKEUP_IRQ_STATUS_I2C1_Pos    (3UL)                     /*!< I2C1 (Bit 3)                                          */
#define SPM_WAKEUP_IRQ_STATUS_I2C1_Msk    (0x8UL)                   /*!< I2C1 (Bitfield-Mask: 0x01)                            */
#define SPM_WAKEUP_IRQ_STATUS_SPI0_Pos    (4UL)                     /*!< SPI0 (Bit 4)                                          */
#define SPM_WAKEUP_IRQ_STATUS_SPI0_Msk    (0x10UL)                  /*!< SPI0 (Bitfield-Mask: 0x01)                            */
#define SPM_WAKEUP_IRQ_STATUS_SPI1_Pos    (5UL)                     /*!< SPI1 (Bit 5)                                          */
#define SPM_WAKEUP_IRQ_STATUS_SPI1_Msk    (0x20UL)                  /*!< SPI1 (Bitfield-Mask: 0x01)                            */
#define SPM_WAKEUP_IRQ_STATUS_CAN0_Pos    (7UL)                     /*!< CAN0 (Bit 7)                                          */
#define SPM_WAKEUP_IRQ_STATUS_CAN0_Msk    (0x80UL)                  /*!< CAN0 (Bitfield-Mask: 0x01)                            */
#define SPM_WAKEUP_IRQ_STATUS_UART0_Pos   (9UL)                     /*!< UART0 (Bit 9)                                         */
#define SPM_WAKEUP_IRQ_STATUS_UART0_Msk   (0x200UL)                 /*!< UART0 (Bitfield-Mask: 0x01)                           */
#define SPM_WAKEUP_IRQ_STATUS_UART1_Pos   (10UL)                    /*!< UART1 (Bit 10)                                        */
#define SPM_WAKEUP_IRQ_STATUS_UART1_Msk   (0x400UL)                 /*!< UART1 (Bitfield-Mask: 0x01)                           */
#define SPM_WAKEUP_IRQ_STATUS_UART2_Pos   (11UL)                    /*!< UART2 (Bit 11)                                        */
#define SPM_WAKEUP_IRQ_STATUS_UART2_Msk   (0x800UL)                 /*!< UART2 (Bitfield-Mask: 0x01)                           */
#define SPM_WAKEUP_IRQ_STATUS_RTC_Pos     (15UL)                    /*!< RTC (Bit 15)                                         */
#define SPM_WAKEUP_IRQ_STATUS_RTC_Msk     (0x8000UL)                /*!< RTC (Bitfield-Mask: 0x01)                            */
#define SPM_WAKEUP_IRQ_STATUS_ADC0_Pos    (16UL)                    /*!< ADC0 (Bit 16)                                         */
#define SPM_WAKEUP_IRQ_STATUS_ADC0_Msk    (0x10000UL)               /*!< ADC0 (Bitfield-Mask: 0x01)                            */
#define SPM_WAKEUP_IRQ_STATUS_GPIO_Pos    (17UL)                    /*!< GPIO (Bit 17)                                         */
#define SPM_WAKEUP_IRQ_STATUS_GPIO_Msk    (0x20000UL)               /*!< GPIO (Bitfield-Mask: 0x01)                            */
#define SPM_WAKEUP_IRQ_STATUS_NMI_Pos     (18UL)                    /*!< NMI (Bit 18)                                          */
#define SPM_WAKEUP_IRQ_STATUS_NMI_Msk     (0x40000UL)               /*!< NMI (Bitfield-Mask: 0x01)                             */
#define SPM_WAKEUP_IRQ_STATUS_PVD_Pos     (19UL)                    /*!< PVD (Bit 19)                                          */
#define SPM_WAKEUP_IRQ_STATUS_PVD_Msk     (0x80000UL)               /*!< PVD (Bitfield-Mask: 0x01)                             */
#define SPM_WAKEUP_IRQ_STATUS_OVER_COUNT_Pos (20UL)                 /*!< OVER_COUNT (Bit 20)                                   */
#define SPM_WAKEUP_IRQ_STATUS_OVER_COUNT_Msk (0x100000UL)           /*!< OVER_COUNT (Bitfield-Mask: 0x01)                      */


/* =========================================================================================================================== */
/* ================                                           GPIO                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define GPIO_CR_MODE0_Pos                 (0UL)                     /*!< MODE0 (Bit 0)                                         */
#define GPIO_CR_MODE0_Msk                 (0x1UL)                   /*!< MODE0 (Bitfield-Mask: 0x01)                           */
#define GPIO_CR_MODE1_Pos                 (1UL)                     /*!< MODE1 (Bit 1)                                         */
#define GPIO_CR_MODE1_Msk                 (0x2UL)                   /*!< MODE1 (Bitfield-Mask: 0x01)                           */
#define GPIO_CR_MODE2_Pos                 (2UL)                     /*!< MODE2 (Bit 2)                                         */
#define GPIO_CR_MODE2_Msk                 (0x4UL)                   /*!< MODE2 (Bitfield-Mask: 0x01)                           */
#define GPIO_CR_MODE3_Pos                 (3UL)                     /*!< MODE3 (Bit 3)                                         */
#define GPIO_CR_MODE3_Msk                 (0x8UL)                   /*!< MODE3 (Bitfield-Mask: 0x01)                           */
#define GPIO_CR_MODE4_Pos                 (4UL)                     /*!< MODE4 (Bit 4)                                         */
#define GPIO_CR_MODE4_Msk                 (0x10UL)                  /*!< MODE4 (Bitfield-Mask: 0x01)                           */
#define GPIO_CR_MODE5_Pos                 (5UL)                     /*!< MODE5 (Bit 5)                                         */
#define GPIO_CR_MODE5_Msk                 (0x20UL)                  /*!< MODE5 (Bitfield-Mask: 0x01)                           */
#define GPIO_CR_MODE6_Pos                 (6UL)                     /*!< MODE6 (Bit 6)                                         */
#define GPIO_CR_MODE6_Msk                 (0x40UL)                  /*!< MODE6 (Bitfield-Mask: 0x01)                           */
#define GPIO_CR_MODE7_Pos                 (7UL)                     /*!< MODE7 (Bit 7)                                         */
#define GPIO_CR_MODE7_Msk                 (0x80UL)                  /*!< MODE7 (Bitfield-Mask: 0x01)                           */
#define GPIO_CR_MODE8_Pos                 (8UL)                     /*!< MODE8 (Bit 8)                                         */
#define GPIO_CR_MODE8_Msk                 (0x100UL)                 /*!< MODE8 (Bitfield-Mask: 0x01)                           */
#define GPIO_CR_MODE9_Pos                 (9UL)                     /*!< MODE9 (Bit 9)                                         */
#define GPIO_CR_MODE9_Msk                 (0x200UL)                 /*!< MODE9 (Bitfield-Mask: 0x01)                           */
#define GPIO_CR_MODE10_Pos                (10UL)                    /*!< MODE10 (Bit 10)                                       */
#define GPIO_CR_MODE10_Msk                (0x400UL)                 /*!< MODE10 (Bitfield-Mask: 0x01)                          */
#define GPIO_CR_MODE11_Pos                (11UL)                    /*!< MODE11 (Bit 11)                                       */
#define GPIO_CR_MODE11_Msk                (0x800UL)                 /*!< MODE11 (Bitfield-Mask: 0x01)                          */
#define GPIO_CR_MODE12_Pos                (12UL)                    /*!< MODE12 (Bit 12)                                       */
#define GPIO_CR_MODE12_Msk                (0x1000UL)                /*!< MODE12 (Bitfield-Mask: 0x01)                          */
#define GPIO_CR_MODE13_Pos                (13UL)                    /*!< MODE13 (Bit 13)                                       */
#define GPIO_CR_MODE13_Msk                (0x2000UL)                /*!< MODE13 (Bitfield-Mask: 0x01)                          */
#define GPIO_CR_MODE14_Pos                (14UL)                    /*!< MODE14 (Bit 14)                                       */
#define GPIO_CR_MODE14_Msk                (0x4000UL)                /*!< MODE14 (Bitfield-Mask: 0x01)                          */
#define GPIO_CR_MODE15_Pos                (15UL)                    /*!< MODE15 (Bit 15)                                       */
#define GPIO_CR_MODE15_Msk                (0x8000UL)                /*!< MODE15 (Bitfield-Mask: 0x01)                          */
#define GPIO_CR_Pos(x)                    ((uint32_t)x)             /*!< MODEx  (Bit x)                                        */
#define GPIO_CR_Msk(x)                    (0x01UL<<GPIO_CR_Pos(x))  /*!< MODEx  (Bitfield-Mask: 0x01)                          */
/* ==========================================================  IDR  ========================================================== */
#define GPIO_IDR_IDR0_Pos                 (0UL)                     /*!< IDR0 (Bit 0)                                          */
#define GPIO_IDR_IDR0_Msk                 (0x1UL)                   /*!< IDR0 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR1_Pos                 (1UL)                     /*!< IDR1 (Bit 1)                                          */
#define GPIO_IDR_IDR1_Msk                 (0x2UL)                   /*!< IDR1 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR2_Pos                 (2UL)                     /*!< IDR2 (Bit 2)                                          */
#define GPIO_IDR_IDR2_Msk                 (0x4UL)                   /*!< IDR2 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR3_Pos                 (3UL)                     /*!< IDR3 (Bit 3)                                          */
#define GPIO_IDR_IDR3_Msk                 (0x8UL)                   /*!< IDR3 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR4_Pos                 (4UL)                     /*!< IDR4 (Bit 4)                                          */
#define GPIO_IDR_IDR4_Msk                 (0x10UL)                  /*!< IDR4 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR5_Pos                 (5UL)                     /*!< IDR5 (Bit 5)                                          */
#define GPIO_IDR_IDR5_Msk                 (0x20UL)                  /*!< IDR5 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR6_Pos                 (6UL)                     /*!< IDR6 (Bit 6)                                          */
#define GPIO_IDR_IDR6_Msk                 (0x40UL)                  /*!< IDR6 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR7_Pos                 (7UL)                     /*!< IDR7 (Bit 7)                                          */
#define GPIO_IDR_IDR7_Msk                 (0x80UL)                  /*!< IDR7 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR8_Pos                 (8UL)                     /*!< IDR8 (Bit 8)                                          */
#define GPIO_IDR_IDR8_Msk                 (0x100UL)                 /*!< IDR8 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR9_Pos                 (9UL)                     /*!< IDR9 (Bit 9)                                          */
#define GPIO_IDR_IDR9_Msk                 (0x200UL)                 /*!< IDR9 (Bitfield-Mask: 0x01)                            */
#define GPIO_IDR_IDR10_Pos                (10UL)                    /*!< IDR10 (Bit 10)                                        */
#define GPIO_IDR_IDR10_Msk                (0x400UL)                 /*!< IDR10 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR11_Pos                (11UL)                    /*!< IDR11 (Bit 11)                                        */
#define GPIO_IDR_IDR11_Msk                (0x800UL)                 /*!< IDR11 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR12_Pos                (12UL)                    /*!< IDR12 (Bit 12)                                        */
#define GPIO_IDR_IDR12_Msk                (0x1000UL)                /*!< IDR12 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR13_Pos                (13UL)                    /*!< IDR13 (Bit 13)                                        */
#define GPIO_IDR_IDR13_Msk                (0x2000UL)                /*!< IDR13 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR14_Pos                (14UL)                    /*!< IDR14 (Bit 14)                                        */
#define GPIO_IDR_IDR14_Msk                (0x4000UL)                /*!< IDR14 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_IDR15_Pos                (15UL)                    /*!< IDR15 (Bit 15)                                        */
#define GPIO_IDR_IDR15_Msk                (0x8000UL)                /*!< IDR15 (Bitfield-Mask: 0x01)                           */
#define GPIO_IDR_Pos(x)                   ((uint32_t)x)             /*!< IDRx  (Bit x)                                         */
#define GPIO_IDR_Msk(x)                   (0x01UL<<GPIO_IDR_Pos(x)) /*!< IDRx  (Bitfield-Mask: 0x01)                           */
/* ==========================================================  ODR  ========================================================== */
#define GPIO_ODR_ODR0_Pos                 (0UL)                     /*!< ODR0 (Bit 0)                                          */
#define GPIO_ODR_ODR0_Msk                 (0x1UL)                   /*!< ODR0 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR1_Pos                 (1UL)                     /*!< ODR1 (Bit 1)                                          */
#define GPIO_ODR_ODR1_Msk                 (0x2UL)                   /*!< ODR1 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR2_Pos                 (2UL)                     /*!< ODR2 (Bit 2)                                          */
#define GPIO_ODR_ODR2_Msk                 (0x4UL)                   /*!< ODR2 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR3_Pos                 (3UL)                     /*!< ODR3 (Bit 3)                                          */
#define GPIO_ODR_ODR3_Msk                 (0x8UL)                   /*!< ODR3 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR4_Pos                 (4UL)                     /*!< ODR4 (Bit 4)                                          */
#define GPIO_ODR_ODR4_Msk                 (0x10UL)                  /*!< ODR4 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR5_Pos                 (5UL)                     /*!< ODR5 (Bit 5)                                          */
#define GPIO_ODR_ODR5_Msk                 (0x20UL)                  /*!< ODR5 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR6_Pos                 (6UL)                     /*!< ODR6 (Bit 6)                                          */
#define GPIO_ODR_ODR6_Msk                 (0x40UL)                  /*!< ODR6 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR7_Pos                 (7UL)                     /*!< ODR7 (Bit 7)                                          */
#define GPIO_ODR_ODR7_Msk                 (0x80UL)                  /*!< ODR7 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR8_Pos                 (8UL)                     /*!< ODR8 (Bit 8)                                          */
#define GPIO_ODR_ODR8_Msk                 (0x100UL)                 /*!< ODR8 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR9_Pos                 (9UL)                     /*!< ODR9 (Bit 9)                                          */
#define GPIO_ODR_ODR9_Msk                 (0x200UL)                 /*!< ODR9 (Bitfield-Mask: 0x01)                            */
#define GPIO_ODR_ODR10_Pos                (10UL)                    /*!< ODR10 (Bit 10)                                        */
#define GPIO_ODR_ODR10_Msk                (0x400UL)                 /*!< ODR10 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR11_Pos                (11UL)                    /*!< ODR11 (Bit 11)                                        */
#define GPIO_ODR_ODR11_Msk                (0x800UL)                 /*!< ODR11 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR12_Pos                (12UL)                    /*!< ODR12 (Bit 12)                                        */
#define GPIO_ODR_ODR12_Msk                (0x1000UL)                /*!< ODR12 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR13_Pos                (13UL)                    /*!< ODR13 (Bit 13)                                        */
#define GPIO_ODR_ODR13_Msk                (0x2000UL)                /*!< ODR13 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR14_Pos                (14UL)                    /*!< ODR14 (Bit 14)                                        */
#define GPIO_ODR_ODR14_Msk                (0x4000UL)                /*!< ODR14 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_ODR15_Pos                (15UL)                    /*!< ODR15 (Bit 15)                                        */
#define GPIO_ODR_ODR15_Msk                (0x8000UL)                /*!< ODR15 (Bitfield-Mask: 0x01)                           */
#define GPIO_ODR_Pos(x)                   ((uint32_t)x)             /*!< ODRx  (Bit x)                                         */
#define GPIO_ODR_Msk(x)                   (0x01UL<<GPIO_ODR_Pos(x)) /*!< ODRx  (Bitfield-Mask: 0x01)                           */
/* =========================================================  BSRR  ========================================================== */
#define GPIO_BSRR_BS0_Pos                 (0UL)                     /*!< BS0 (Bit 0)                                           */
#define GPIO_BSRR_BS0_Msk                 (0x1UL)                   /*!< BS0 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BS1_Pos                 (1UL)                     /*!< BS1 (Bit 1)                                           */
#define GPIO_BSRR_BS1_Msk                 (0x2UL)                   /*!< BS1 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BS2_Pos                 (2UL)                     /*!< BS2 (Bit 2)                                           */
#define GPIO_BSRR_BS2_Msk                 (0x4UL)                   /*!< BS2 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BS3_Pos                 (3UL)                     /*!< BS3 (Bit 3)                                           */
#define GPIO_BSRR_BS3_Msk                 (0x8UL)                   /*!< BS3 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BS4_Pos                 (4UL)                     /*!< BS4 (Bit 4)                                           */
#define GPIO_BSRR_BS4_Msk                 (0x10UL)                  /*!< BS4 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BS5_Pos                 (5UL)                     /*!< BS5 (Bit 5)                                           */
#define GPIO_BSRR_BS5_Msk                 (0x20UL)                  /*!< BS5 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BS6_Pos                 (6UL)                     /*!< BS6 (Bit 6)                                           */
#define GPIO_BSRR_BS6_Msk                 (0x40UL)                  /*!< BS6 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BS7_Pos                 (7UL)                     /*!< BS7 (Bit 7)                                           */
#define GPIO_BSRR_BS7_Msk                 (0x80UL)                  /*!< BS7 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BS8_Pos                 (8UL)                     /*!< BS8 (Bit 8)                                           */
#define GPIO_BSRR_BS8_Msk                 (0x100UL)                 /*!< BS8 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BS9_Pos                 (9UL)                     /*!< BS9 (Bit 9)                                           */
#define GPIO_BSRR_BS9_Msk                 (0x200UL)                 /*!< BS9 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BS10_Pos                (10UL)                    /*!< BS10 (Bit 10)                                         */
#define GPIO_BSRR_BS10_Msk                (0x400UL)                 /*!< BS10 (Bitfield-Mask: 0x01)                            */
#define GPIO_BSRR_BS11_Pos                (11UL)                    /*!< BS11 (Bit 11)                                         */
#define GPIO_BSRR_BS11_Msk                (0x800UL)                 /*!< BS11 (Bitfield-Mask: 0x01)                            */
#define GPIO_BSRR_BS12_Pos                (12UL)                    /*!< BS12 (Bit 12)                                         */
#define GPIO_BSRR_BS12_Msk                (0x1000UL)                /*!< BS12 (Bitfield-Mask: 0x01)                            */
#define GPIO_BSRR_BS13_Pos                (13UL)                    /*!< BS13 (Bit 13)                                         */
#define GPIO_BSRR_BS13_Msk                (0x2000UL)                /*!< BS13 (Bitfield-Mask: 0x01)                            */
#define GPIO_BSRR_BS14_Pos                (14UL)                    /*!< BS14 (Bit 14)                                         */
#define GPIO_BSRR_BS14_Msk                (0x4000UL)                /*!< BS14 (Bitfield-Mask: 0x01)                            */
#define GPIO_BSRR_BS15_Pos                (15UL)                    /*!< BS15 (Bit 15)                                         */
#define GPIO_BSRR_BS15_Msk                (0x8000UL)                /*!< BS15 (Bitfield-Mask: 0x01)                            */
#define GPIO_BSRR_BR0_Pos                 (16UL)                    /*!< BR0 (Bit 16)                                          */
#define GPIO_BSRR_BR0_Msk                 (0x10000UL)               /*!< BR0 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BR1_Pos                 (17UL)                    /*!< BR1 (Bit 17)                                          */
#define GPIO_BSRR_BR1_Msk                 (0x20000UL)               /*!< BR1 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BR2_Pos                 (18UL)                    /*!< BR2 (Bit 18)                                          */
#define GPIO_BSRR_BR2_Msk                 (0x40000UL)               /*!< BR2 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BR3_Pos                 (19UL)                    /*!< BR3 (Bit 19)                                          */
#define GPIO_BSRR_BR3_Msk                 (0x80000UL)               /*!< BR3 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BR4_Pos                 (20UL)                    /*!< BR4 (Bit 20)                                          */
#define GPIO_BSRR_BR4_Msk                 (0x100000UL)              /*!< BR4 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BR5_Pos                 (21UL)                    /*!< BR5 (Bit 21)                                          */
#define GPIO_BSRR_BR5_Msk                 (0x200000UL)              /*!< BR5 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BR6_Pos                 (22UL)                    /*!< BR6 (Bit 22)                                          */
#define GPIO_BSRR_BR6_Msk                 (0x400000UL)              /*!< BR6 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BR7_Pos                 (23UL)                    /*!< BR7 (Bit 23)                                          */
#define GPIO_BSRR_BR7_Msk                 (0x800000UL)              /*!< BR7 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BR8_Pos                 (24UL)                    /*!< BR8 (Bit 24)                                          */
#define GPIO_BSRR_BR8_Msk                 (0x1000000UL)             /*!< BR8 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BR9_Pos                 (25UL)                    /*!< BR9 (Bit 25)                                          */
#define GPIO_BSRR_BR9_Msk                 (0x2000000UL)             /*!< BR9 (Bitfield-Mask: 0x01)                             */
#define GPIO_BSRR_BR10_Pos                (26UL)                    /*!< BR10 (Bit 26)                                         */
#define GPIO_BSRR_BR10_Msk                (0x4000000UL)             /*!< BR10 (Bitfield-Mask: 0x01)                            */
#define GPIO_BSRR_BR11_Pos                (27UL)                    /*!< BR11 (Bit 27)                                         */
#define GPIO_BSRR_BR11_Msk                (0x8000000UL)             /*!< BR11 (Bitfield-Mask: 0x01)                            */
#define GPIO_BSRR_BR12_Pos                (28UL)                    /*!< BR12 (Bit 28)                                         */
#define GPIO_BSRR_BR12_Msk                (0x10000000UL)            /*!< BR12 (Bitfield-Mask: 0x01)                            */
#define GPIO_BSRR_BR13_Pos                (29UL)                    /*!< BR13 (Bit 29)                                         */
#define GPIO_BSRR_BR13_Msk                (0x20000000UL)            /*!< BR13 (Bitfield-Mask: 0x01)                            */
#define GPIO_BSRR_BR14_Pos                (30UL)                    /*!< BR14 (Bit 30)                                         */
#define GPIO_BSRR_BR14_Msk                (0x40000000UL)            /*!< BR14 (Bitfield-Mask: 0x01)                            */
#define GPIO_BSRR_BR15_Pos                (31UL)                    /*!< BR15 (Bit 31)                                         */
#define GPIO_BSRR_BR15_Msk                (0x80000000UL)            /*!< BR15 (Bitfield-Mask: 0x01)                            */
#define GPIO_BSRR_BS_Pos(x)               ((uint32_t)x)             /*!< BSx  (Bit x)                                          */
#define GPIO_BSRR_BS_Msk(x)               (0x01UL<<GPIO_BSRR_BS_Pos(x))  /*!< BSx  (Bitfield-Mask: 0x01)                       */
#define GPIO_BSRR_BR_Pos(x)               (16UL+((uint32_t)x))           /*!< BRx  (Bit 16+x)                                       */
#define GPIO_BSRR_BR_Msk(x)               (0x01UL<<GPIO_BSRR_BR_Pos(x))  /*!< BRx  (Bitfield-Mask: 0x01)                       */
/* ==========================================================  BRR  ========================================================== */
#define GPIO_BRR_BR0_Pos                  (0UL)                     /*!< BR0 (Bit 0)                                           */
#define GPIO_BRR_BR0_Msk                  (0x1UL)                   /*!< BR0 (Bitfield-Mask: 0x01)                             */
#define GPIO_BRR_BR1_Pos                  (1UL)                     /*!< BR1 (Bit 1)                                           */
#define GPIO_BRR_BR1_Msk                  (0x2UL)                   /*!< BR1 (Bitfield-Mask: 0x01)                             */
#define GPIO_BRR_BR2_Pos                  (2UL)                     /*!< BR2 (Bit 2)                                           */
#define GPIO_BRR_BR2_Msk                  (0x4UL)                   /*!< BR2 (Bitfield-Mask: 0x01)                             */
#define GPIO_BRR_BR3_Pos                  (3UL)                     /*!< BR3 (Bit 3)                                           */
#define GPIO_BRR_BR3_Msk                  (0x8UL)                   /*!< BR3 (Bitfield-Mask: 0x01)                             */
#define GPIO_BRR_BR4_Pos                  (4UL)                     /*!< BR4 (Bit 4)                                           */
#define GPIO_BRR_BR4_Msk                  (0x10UL)                  /*!< BR4 (Bitfield-Mask: 0x01)                             */
#define GPIO_BRR_BR5_Pos                  (5UL)                     /*!< BR5 (Bit 5)                                           */
#define GPIO_BRR_BR5_Msk                  (0x20UL)                  /*!< BR5 (Bitfield-Mask: 0x01)                             */
#define GPIO_BRR_BR6_Pos                  (6UL)                     /*!< BR6 (Bit 6)                                           */
#define GPIO_BRR_BR6_Msk                  (0x40UL)                  /*!< BR6 (Bitfield-Mask: 0x01)                             */
#define GPIO_BRR_BR7_Pos                  (7UL)                     /*!< BR7 (Bit 7)                                           */
#define GPIO_BRR_BR7_Msk                  (0x80UL)                  /*!< BR7 (Bitfield-Mask: 0x01)                             */
#define GPIO_BRR_BR8_Pos                  (8UL)                     /*!< BR8 (Bit 8)                                           */
#define GPIO_BRR_BR8_Msk                  (0x100UL)                 /*!< BR8 (Bitfield-Mask: 0x01)                             */
#define GPIO_BRR_BR9_Pos                  (9UL)                     /*!< BR9 (Bit 9)                                           */
#define GPIO_BRR_BR9_Msk                  (0x200UL)                 /*!< BR9 (Bitfield-Mask: 0x01)                             */
#define GPIO_BRR_BR10_Pos                 (10UL)                    /*!< BR10 (Bit 10)                                         */
#define GPIO_BRR_BR10_Msk                 (0x400UL)                 /*!< BR10 (Bitfield-Mask: 0x01)                            */
#define GPIO_BRR_BR11_Pos                 (11UL)                    /*!< BR11 (Bit 11)                                         */
#define GPIO_BRR_BR11_Msk                 (0x800UL)                 /*!< BR11 (Bitfield-Mask: 0x01)                            */
#define GPIO_BRR_BR12_Pos                 (12UL)                    /*!< BR12 (Bit 12)                                         */
#define GPIO_BRR_BR12_Msk                 (0x1000UL)                /*!< BR12 (Bitfield-Mask: 0x01)                            */
#define GPIO_BRR_BR13_Pos                 (13UL)                    /*!< BR13 (Bit 13)                                         */
#define GPIO_BRR_BR13_Msk                 (0x2000UL)                /*!< BR13 (Bitfield-Mask: 0x01)                            */
#define GPIO_BRR_BR14_Pos                 (14UL)                    /*!< BR14 (Bit 14)                                         */
#define GPIO_BRR_BR14_Msk                 (0x4000UL)                /*!< BR14 (Bitfield-Mask: 0x01)                            */
#define GPIO_BRR_BR15_Pos                 (15UL)                    /*!< BR15 (Bit 15)                                         */
#define GPIO_BRR_BR15_Msk                 (0x8000UL)                /*!< BR15 (Bitfield-Mask: 0x01)                            */
#define GPIO_BRR_BR_Pos(x)                ((uint32_t)x)             /*!< BRx  (Bit x)                                          */
#define GPIO_BRR_BR_Msk(x)                (0x01UL<<GPIO_BRR_BR_Pos(x))  /*!< BRx  (Bitfield-Mask: 0x01)                        */
/* ==========================================================  PD  =========================================================== */
#define GPIO_PD_PD0_Pos                   (0UL)                     /*!< PD0 (Bit 0)                                           */
#define GPIO_PD_PD0_Msk                   (0x1UL)                   /*!< PD0 (Bitfield-Mask: 0x01)                             */
#define GPIO_PD_PD1_Pos                   (1UL)                     /*!< PD1 (Bit 1)                                           */
#define GPIO_PD_PD1_Msk                   (0x2UL)                   /*!< PD1 (Bitfield-Mask: 0x01)                             */
#define GPIO_PD_PD2_Pos                   (2UL)                     /*!< PD2 (Bit 2)                                           */
#define GPIO_PD_PD2_Msk                   (0x4UL)                   /*!< PD2 (Bitfield-Mask: 0x01)                             */
#define GPIO_PD_PD3_Pos                   (3UL)                     /*!< PD3 (Bit 3)                                           */
#define GPIO_PD_PD3_Msk                   (0x8UL)                   /*!< PD3 (Bitfield-Mask: 0x01)                             */
#define GPIO_PD_PD4_Pos                   (4UL)                     /*!< PD4 (Bit 4)                                           */
#define GPIO_PD_PD4_Msk                   (0x10UL)                  /*!< PD4 (Bitfield-Mask: 0x01)                             */
#define GPIO_PD_PD5_Pos                   (5UL)                     /*!< PD5 (Bit 5)                                           */
#define GPIO_PD_PD5_Msk                   (0x20UL)                  /*!< PD5 (Bitfield-Mask: 0x01)                             */
#define GPIO_PD_PD6_Pos                   (6UL)                     /*!< PD6 (Bit 6)                                           */
#define GPIO_PD_PD6_Msk                   (0x40UL)                  /*!< PD6 (Bitfield-Mask: 0x01)                             */
#define GPIO_PD_PD7_Pos                   (7UL)                     /*!< PD7 (Bit 7)                                           */
#define GPIO_PD_PD7_Msk                   (0x80UL)                  /*!< PD7 (Bitfield-Mask: 0x01)                             */
#define GPIO_PD_PD8_Pos                   (8UL)                     /*!< PD8 (Bit 8)                                           */
#define GPIO_PD_PD8_Msk                   (0x100UL)                 /*!< PD8 (Bitfield-Mask: 0x01)                             */
#define GPIO_PD_PD9_Pos                   (9UL)                     /*!< PD9 (Bit 9)                                           */
#define GPIO_PD_PD9_Msk                   (0x200UL)                 /*!< PD9 (Bitfield-Mask: 0x01)                             */
#define GPIO_PD_PD10_Pos                  (10UL)                    /*!< PD10 (Bit 10)                                         */
#define GPIO_PD_PD10_Msk                  (0x400UL)                 /*!< PD10 (Bitfield-Mask: 0x01)                            */
#define GPIO_PD_PD11_Pos                  (11UL)                    /*!< PD11 (Bit 11)                                         */
#define GPIO_PD_PD11_Msk                  (0x800UL)                 /*!< PD11 (Bitfield-Mask: 0x01)                            */
#define GPIO_PD_PD12_Pos                  (12UL)                    /*!< PD12 (Bit 12)                                         */
#define GPIO_PD_PD12_Msk                  (0x1000UL)                /*!< PD12 (Bitfield-Mask: 0x01)                            */
#define GPIO_PD_PD13_Pos                  (13UL)                    /*!< PD13 (Bit 13)                                         */
#define GPIO_PD_PD13_Msk                  (0x2000UL)                /*!< PD13 (Bitfield-Mask: 0x01)                            */
#define GPIO_PD_PD14_Pos                  (14UL)                    /*!< PD14 (Bit 14)                                         */
#define GPIO_PD_PD14_Msk                  (0x4000UL)                /*!< PD14 (Bitfield-Mask: 0x01)                            */
#define GPIO_PD_PD15_Pos                  (15UL)                    /*!< PD15 (Bit 15)                                         */
#define GPIO_PD_PD15_Msk                  (0x8000UL)                /*!< PD15 (Bitfield-Mask: 0x01)                            */
#define GPIO_PD_Pos(x)                    ((uint32_t)x)             /*!< PDx  (Bit x)                                          */
#define GPIO_PD_Msk(x)                    (0x01UL<<GPIO_PD_Pos(x))  /*!< PDx  (Bitfield-Mask: 0x01)                            */
/* ==========================================================  PU  =========================================================== */
#define GPIO_PU_PU0_Pos                   (0UL)                     /*!< PU0 (Bit 0)                                           */
#define GPIO_PU_PU0_Msk                   (0x1UL)                   /*!< PU0 (Bitfield-Mask: 0x01)                             */
#define GPIO_PU_PU1_Pos                   (1UL)                     /*!< PU1 (Bit 1)                                           */
#define GPIO_PU_PU1_Msk                   (0x2UL)                   /*!< PU1 (Bitfield-Mask: 0x01)                             */
#define GPIO_PU_PU2_Pos                   (2UL)                     /*!< PU2 (Bit 2)                                           */
#define GPIO_PU_PU2_Msk                   (0x4UL)                   /*!< PU2 (Bitfield-Mask: 0x01)                             */
#define GPIO_PU_PU3_Pos                   (3UL)                     /*!< PU3 (Bit 3)                                           */
#define GPIO_PU_PU3_Msk                   (0x8UL)                   /*!< PU3 (Bitfield-Mask: 0x01)                             */
#define GPIO_PU_PU4_Pos                   (4UL)                     /*!< PU4 (Bit 4)                                           */
#define GPIO_PU_PU4_Msk                   (0x10UL)                  /*!< PU4 (Bitfield-Mask: 0x01)                             */
#define GPIO_PU_PU5_Pos                   (5UL)                     /*!< PU5 (Bit 5)                                           */
#define GPIO_PU_PU5_Msk                   (0x20UL)                  /*!< PU5 (Bitfield-Mask: 0x01)                             */
#define GPIO_PU_PU6_Pos                   (6UL)                     /*!< PU6 (Bit 6)                                           */
#define GPIO_PU_PU6_Msk                   (0x40UL)                  /*!< PU6 (Bitfield-Mask: 0x01)                             */
#define GPIO_PU_PU7_Pos                   (7UL)                     /*!< PU7 (Bit 7)                                           */
#define GPIO_PU_PU7_Msk                   (0x80UL)                  /*!< PU7 (Bitfield-Mask: 0x01)                             */
#define GPIO_PU_PU8_Pos                   (8UL)                     /*!< PU8 (Bit 8)                                           */
#define GPIO_PU_PU8_Msk                   (0x100UL)                 /*!< PU8 (Bitfield-Mask: 0x01)                             */
#define GPIO_PU_PU9_Pos                   (9UL)                     /*!< PU9 (Bit 9)                                           */
#define GPIO_PU_PU9_Msk                   (0x200UL)                 /*!< PU9 (Bitfield-Mask: 0x01)                             */
#define GPIO_PU_PU10_Pos                  (10UL)                    /*!< PU10 (Bit 10)                                         */
#define GPIO_PU_PU10_Msk                  (0x400UL)                 /*!< PU10 (Bitfield-Mask: 0x01)                            */
#define GPIO_PU_PU11_Pos                  (11UL)                    /*!< PU11 (Bit 11)                                         */
#define GPIO_PU_PU11_Msk                  (0x800UL)                 /*!< PU11 (Bitfield-Mask: 0x01)                            */
#define GPIO_PU_PU12_Pos                  (12UL)                    /*!< PU12 (Bit 12)                                         */
#define GPIO_PU_PU12_Msk                  (0x1000UL)                /*!< PU12 (Bitfield-Mask: 0x01)                            */
#define GPIO_PU_PU13_Pos                  (13UL)                    /*!< PU13 (Bit 13)                                         */
#define GPIO_PU_PU13_Msk                  (0x2000UL)                /*!< PU13 (Bitfield-Mask: 0x01)                            */
#define GPIO_PU_PU14_Pos                  (14UL)                    /*!< PU14 (Bit 14)                                         */
#define GPIO_PU_PU14_Msk                  (0x4000UL)                /*!< PU14 (Bitfield-Mask: 0x01)                            */
#define GPIO_PU_PU15_Pos                  (15UL)                    /*!< PU15 (Bit 15)                                         */
#define GPIO_PU_PU15_Msk                  (0x8000UL)                /*!< PU15 (Bitfield-Mask: 0x01)                            */
#define GPIO_PU_Pos(x)                    ((uint32_t)x)             /*!< PUx  (Bit x)                                          */
#define GPIO_PU_Msk(x)                    (0x01UL<<GPIO_PU_Pos(x))  /*!< PUx  (Bitfield-Mask: 0x01)                            */
/* =========================================================  E4E2  ========================================================== */
#define GPIO_E4E2_E4E2_0_Pos              (0UL)                     /*!< E4E2_0 (Bit 0)                                        */
#define GPIO_E4E2_E4E2_0_Msk              (0x3UL)                   /*!< E4E2_0 (Bitfield-Mask: 0x03)                          */
#define GPIO_E4E2_E4E2_1_Pos              (2UL)                     /*!< E4E2_1 (Bit 2)                                        */
#define GPIO_E4E2_E4E2_1_Msk              (0xcUL)                   /*!< E4E2_1 (Bitfield-Mask: 0x03)                          */
#define GPIO_E4E2_E4E2_2_Pos              (4UL)                     /*!< E4E2_2 (Bit 4)                                        */
#define GPIO_E4E2_E4E2_2_Msk              (0x30UL)                  /*!< E4E2_2 (Bitfield-Mask: 0x03)                          */
#define GPIO_E4E2_E4E2_3_Pos              (6UL)                     /*!< E4E2_3 (Bit 6)                                        */
#define GPIO_E4E2_E4E2_3_Msk              (0xc0UL)                  /*!< E4E2_3 (Bitfield-Mask: 0x03)                          */
#define GPIO_E4E2_E4E2_4_Pos              (8UL)                     /*!< E4E2_4 (Bit 8)                                        */
#define GPIO_E4E2_E4E2_4_Msk              (0x300UL)                 /*!< E4E2_4 (Bitfield-Mask: 0x03)                          */
#define GPIO_E4E2_E4E2_5_Pos              (10UL)                    /*!< E4E2_5 (Bit 10)                                       */
#define GPIO_E4E2_E4E2_5_Msk              (0xc00UL)                 /*!< E4E2_5 (Bitfield-Mask: 0x03)                          */
#define GPIO_E4E2_E4E2_6_Pos              (12UL)                    /*!< E4E2_6 (Bit 12)                                       */
#define GPIO_E4E2_E4E2_6_Msk              (0x3000UL)                /*!< E4E2_6 (Bitfield-Mask: 0x03)                          */
#define GPIO_E4E2_E4E2_7_Pos              (14UL)                    /*!< E4E2_7 (Bit 14)                                       */
#define GPIO_E4E2_E4E2_7_Msk              (0xc000UL)                /*!< E4E2_7 (Bitfield-Mask: 0x03)                          */
#define GPIO_E4E2_E4E2_8_Pos              (16UL)                    /*!< E4E2_8 (Bit 16)                                       */
#define GPIO_E4E2_E4E2_8_Msk              (0x30000UL)               /*!< E4E2_8 (Bitfield-Mask: 0x03)                          */
#define GPIO_E4E2_E4E2_9_Pos              (18UL)                    /*!< E4E2_9 (Bit 18)                                       */
#define GPIO_E4E2_E4E2_9_Msk              (0xc0000UL)               /*!< E4E2_9 (Bitfield-Mask: 0x03)                          */
#define GPIO_E4E2_E4E2_10_Pos             (20UL)                    /*!< E4E2_10 (Bit 20)                                      */
#define GPIO_E4E2_E4E2_10_Msk             (0x300000UL)              /*!< E4E2_10 (Bitfield-Mask: 0x03)                         */
#define GPIO_E4E2_E4E2_11_Pos             (22UL)                    /*!< E4E2_11 (Bit 22)                                      */
#define GPIO_E4E2_E4E2_11_Msk             (0xc00000UL)              /*!< E4E2_11 (Bitfield-Mask: 0x03)                         */
#define GPIO_E4E2_E4E2_12_Pos             (24UL)                    /*!< E4E2_12 (Bit 24)                                      */
#define GPIO_E4E2_E4E2_12_Msk             (0x3000000UL)             /*!< E4E2_12 (Bitfield-Mask: 0x03)                         */
#define GPIO_E4E2_E4E2_13_Pos             (26UL)                    /*!< E4E2_13 (Bit 26)                                      */
#define GPIO_E4E2_E4E2_13_Msk             (0xc000000UL)             /*!< E4E2_13 (Bitfield-Mask: 0x03)                         */
#define GPIO_E4E2_E4E2_14_Pos             (28UL)                    /*!< E4E2_14 (Bit 28)                                      */
#define GPIO_E4E2_E4E2_14_Msk             (0x30000000UL)            /*!< E4E2_14 (Bitfield-Mask: 0x03)                         */
#define GPIO_E4E2_E4E2_15_Pos             (30UL)                    /*!< E4E2_15 (Bit 30)                                      */
#define GPIO_E4E2_E4E2_15_Msk             (0xc0000000UL)            /*!< E4E2_15 (Bitfield-Mask: 0x03)                         */
#define GPIO_E4E2_Pos(x)                  (2UL*((uint32_t)x))                 /*!< PUx  (Bit 2*x)                                        */
#define GPIO_E4E2_Msk(x)                  (0x03UL<<GPIO_E4E2_Pos(x))  /*!< PUx  (Bitfield-Mask: 0x03)                          */

/* =========================================================================================================================== */
/* ================                                           PMUX                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  PINMUX  ======================================================== */
#define PMUX_PINMUX_PINMUX0_Pos          (0UL)                     /*!< PINMUX0 (Bit 0)                                       */
#define PMUX_PINMUX_PINMUX0_Msk          (0x7UL)                   /*!< PINMUX0 (Bitfield-Mask: 0x07)                         */
#define PMUX_PINMUX_PINMUX1_Pos          (3UL)                     /*!< PINMUX1 (Bit 3)                                       */
#define PMUX_PINMUX_PINMUX1_Msk          (0x38UL)                  /*!< PINMUX1 (Bitfield-Mask: 0x07)                         */
#define PMUX_PINMUX_PINMUX2_Pos          (6UL)                     /*!< PINMUX2 (Bit 6)                                       */
#define PMUX_PINMUX_PINMUX2_Msk          (0x1c0UL)                 /*!< PINMUX2 (Bitfield-Mask: 0x07)                         */
#define PMUX_PINMUX_PINMUX3_Pos          (9UL)                     /*!< PINMUX3 (Bit 9)                                       */
#define PMUX_PINMUX_PINMUX3_Msk          (0xe00UL)                 /*!< PINMUX3 (Bitfield-Mask: 0x07)                         */
#define PMUX_PINMUX_PINMUX4_Pos          (12UL)                    /*!< PINMUX4 (Bit 12)                                      */
#define PMUX_PINMUX_PINMUX4_Msk          (0x7000UL)                /*!< PINMUX4 (Bitfield-Mask: 0x07)                         */
#define PMUX_PINMUX_PINMUX5_Pos          (15UL)                    /*!< PINMUX5 (Bit 15)                                      */
#define PMUX_PINMUX_PINMUX5_Msk          (0x38000UL)               /*!< PINMUX5 (Bitfield-Mask: 0x07)                         */
#define PMUX_PINMUX_PINMUX6_Pos          (18UL)                    /*!< PINMUX6 (Bit 18)                                      */
#define PMUX_PINMUX_PINMUX6_Msk          (0x1c0000UL)              /*!< PINMUX6 (Bitfield-Mask: 0x07)                         */
#define PMUX_PINMUX_PINMUX7_Pos          (21UL)                    /*!< PINMUX7 (Bit 21)                                      */
#define PMUX_PINMUX_PINMUX7_Msk          (0xe00000UL)              /*!< PINMUX7 (Bitfield-Mask: 0x07)                         */
#define PMUX_PINMUX_PINMUX8_Pos          (24UL)                    /*!< PINMUX8 (Bit 24)                                      */
#define PMUX_PINMUX_PINMUX8_Msk          (0x7000000UL)             /*!< PINMUX8 (Bitfield-Mask: 0x07)                         */
#define PMUX_PINMUX_PINMUX9_Pos          (27UL)                    /*!< PINMUX9 (Bit 27)                                      */
#define PMUX_PINMUX_PINMUX9_Msk          (0x38000000UL)            /*!< PINMUX9 (Bitfield-Mask: 0x07)                         */
#define PMUX_PINMUX_Pos(x)               (3UL*((uint32_t)x))       /*!< PINMUXx (Bitfield-Mask: 0x07)                         */
#define PMUX_PINMUX_Msk(x)               ((0x07UL)<<(PMUX_PINMUX_Pos(x)))  /*!< PINMUXx (Bitfield-Mask: 0x07)                 */


/* =========================================================================================================================== */
/* ================                                           EXTI                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  PR  =========================================================== */
#define EXTI_PR_PR0_Pos                   (0UL)                     /*!< PR0 (Bit 0)                                           */
#define EXTI_PR_PR0_Msk                   (0x1UL)                   /*!< PR0 (Bitfield-Mask: 0x01)                             */
#define EXTI_PR_PR1_Pos                   (1UL)                     /*!< PR1 (Bit 1)                                           */
#define EXTI_PR_PR1_Msk                   (0x2UL)                   /*!< PR1 (Bitfield-Mask: 0x01)                             */
#define EXTI_PR_PR2_Pos                   (2UL)                     /*!< PR2 (Bit 2)                                           */
#define EXTI_PR_PR2_Msk                   (0x4UL)                   /*!< PR2 (Bitfield-Mask: 0x01)                             */
#define EXTI_PR_PR3_Pos                   (3UL)                     /*!< PR3 (Bit 3)                                           */
#define EXTI_PR_PR3_Msk                   (0x8UL)                   /*!< PR3 (Bitfield-Mask: 0x01)                             */
#define EXTI_PR_PR4_Pos                   (4UL)                     /*!< PR4 (Bit 4)                                           */
#define EXTI_PR_PR4_Msk                   (0x10UL)                  /*!< PR4 (Bitfield-Mask: 0x01)                             */
#define EXTI_PR_PR5_Pos                   (5UL)                     /*!< PR5 (Bit 5)                                           */
#define EXTI_PR_PR5_Msk                   (0x20UL)                  /*!< PR5 (Bitfield-Mask: 0x01)                             */
#define EXTI_PR_PR6_Pos                   (6UL)                     /*!< PR6 (Bit 6)                                           */
#define EXTI_PR_PR6_Msk                   (0x40UL)                  /*!< PR6 (Bitfield-Mask: 0x01)                             */
#define EXTI_PR_PR7_Pos                   (7UL)                     /*!< PR7 (Bit 7)                                           */
#define EXTI_PR_PR7_Msk                   (0x80UL)                  /*!< PR7 (Bitfield-Mask: 0x01)                             */
#define EXTI_PR_PR8_Pos                   (8UL)                     /*!< PR8 (Bit 8)                                           */
#define EXTI_PR_PR8_Msk                   (0x100UL)                 /*!< PR8 (Bitfield-Mask: 0x01)                             */
#define EXTI_PR_PR9_Pos                   (9UL)                     /*!< PR9 (Bit 9)                                           */
#define EXTI_PR_PR9_Msk                   (0x200UL)                 /*!< PR9 (Bitfield-Mask: 0x01)                             */
#define EXTI_PR_PR10_Pos                  (10UL)                    /*!< PR10 (Bit 10)                                         */
#define EXTI_PR_PR10_Msk                  (0x400UL)                 /*!< PR10 (Bitfield-Mask: 0x01)                            */
#define EXTI_PR_PR11_Pos                  (11UL)                    /*!< PR11 (Bit 11)                                         */
#define EXTI_PR_PR11_Msk                  (0x800UL)                 /*!< PR11 (Bitfield-Mask: 0x01)                            */
#define EXTI_PR_PR12_Pos                  (12UL)                    /*!< PR12 (Bit 12)                                         */
#define EXTI_PR_PR12_Msk                  (0x1000UL)                /*!< PR12 (Bitfield-Mask: 0x01)                            */
#define EXTI_PR_PR13_Pos                  (13UL)                    /*!< PR13 (Bit 13)                                         */
#define EXTI_PR_PR13_Msk                  (0x2000UL)                /*!< PR13 (Bitfield-Mask: 0x01)                            */
#define EXTI_PR_PR14_Pos                  (14UL)                    /*!< PR14 (Bit 14)                                         */
#define EXTI_PR_PR14_Msk                  (0x4000UL)                /*!< PR14 (Bitfield-Mask: 0x01)                            */
#define EXTI_PR_PR15_Pos                  (15UL)                    /*!< PR15 (Bit 15)                                         */
#define EXTI_PR_PR15_Msk                  (0x8000UL)                /*!< PR15 (Bitfield-Mask: 0x01)                            */
#define EXTI_PR_Pos(x)                    ((uint32_t)x)             /*!< PRx  (Bit x)                                          */
#define EXTI_PR_Msk(x)                    (0x1UL<<EXTI_PR_Pos(x))   /*!< PRx  (Bitfield-Mask: 0x01)                            */
/* ==========================================================  IMR  ========================================================== */
#define EXTI_IMR_IMR0_Pos                 (0UL)                     /*!< IMR0 (Bit 0)                                          */
#define EXTI_IMR_IMR0_Msk                 (0x1UL)                   /*!< IMR0 (Bitfield-Mask: 0x01)                            */
#define EXTI_IMR_IMR1_Pos                 (1UL)                     /*!< IMR1 (Bit 1)                                          */
#define EXTI_IMR_IMR1_Msk                 (0x2UL)                   /*!< IMR1 (Bitfield-Mask: 0x01)                            */
#define EXTI_IMR_IMR2_Pos                 (2UL)                     /*!< IMR2 (Bit 2)                                          */
#define EXTI_IMR_IMR2_Msk                 (0x4UL)                   /*!< IMR2 (Bitfield-Mask: 0x01)                            */
#define EXTI_IMR_IMR3_Pos                 (3UL)                     /*!< IMR3 (Bit 3)                                          */
#define EXTI_IMR_IMR3_Msk                 (0x8UL)                   /*!< IMR3 (Bitfield-Mask: 0x01)                            */
#define EXTI_IMR_IMR4_Pos                 (4UL)                     /*!< IMR4 (Bit 4)                                          */
#define EXTI_IMR_IMR4_Msk                 (0x10UL)                  /*!< IMR4 (Bitfield-Mask: 0x01)                            */
#define EXTI_IMR_IMR5_Pos                 (5UL)                     /*!< IMR5 (Bit 5)                                          */
#define EXTI_IMR_IMR5_Msk                 (0x20UL)                  /*!< IMR5 (Bitfield-Mask: 0x01)                            */
#define EXTI_IMR_IMR6_Pos                 (6UL)                     /*!< IMR6 (Bit 6)                                          */
#define EXTI_IMR_IMR6_Msk                 (0x40UL)                  /*!< IMR6 (Bitfield-Mask: 0x01)                            */
#define EXTI_IMR_IMR7_Pos                 (7UL)                     /*!< IMR7 (Bit 7)                                          */
#define EXTI_IMR_IMR7_Msk                 (0x80UL)                  /*!< IMR7 (Bitfield-Mask: 0x01)                            */
#define EXTI_IMR_IMR8_Pos                 (8UL)                     /*!< IMR8 (Bit 8)                                          */
#define EXTI_IMR_IMR8_Msk                 (0x100UL)                 /*!< IMR8 (Bitfield-Mask: 0x01)                            */
#define EXTI_IMR_IMR9_Pos                 (9UL)                     /*!< IMR9 (Bit 9)                                          */
#define EXTI_IMR_IMR9_Msk                 (0x200UL)                 /*!< IMR9 (Bitfield-Mask: 0x01)                            */
#define EXTI_IMR_IMR10_Pos                (10UL)                    /*!< IMR10 (Bit 10)                                        */
#define EXTI_IMR_IMR10_Msk                (0x400UL)                 /*!< IMR10 (Bitfield-Mask: 0x01)                           */
#define EXTI_IMR_IMR11_Pos                (11UL)                    /*!< IMR11 (Bit 11)                                        */
#define EXTI_IMR_IMR11_Msk                (0x800UL)                 /*!< IMR11 (Bitfield-Mask: 0x01)                           */
#define EXTI_IMR_IMR12_Pos                (12UL)                    /*!< IMR12 (Bit 12)                                        */
#define EXTI_IMR_IMR12_Msk                (0x1000UL)                /*!< IMR12 (Bitfield-Mask: 0x01)                           */
#define EXTI_IMR_IMR13_Pos                (13UL)                    /*!< IMR13 (Bit 13)                                        */
#define EXTI_IMR_IMR13_Msk                (0x2000UL)                /*!< IMR13 (Bitfield-Mask: 0x01)                           */
#define EXTI_IMR_IMR14_Pos                (14UL)                    /*!< IMR14 (Bit 14)                                        */
#define EXTI_IMR_IMR14_Msk                (0x4000UL)                /*!< IMR14 (Bitfield-Mask: 0x01)                           */
#define EXTI_IMR_IMR15_Pos                (15UL)                    /*!< IMR15 (Bit 15)                                        */
#define EXTI_IMR_IMR15_Msk                (0x8000UL)                /*!< IMR15 (Bitfield-Mask: 0x01)                           */
#define EXTI_IMR_Pos(x)                   ((uint32_t)x)             /*!< IMRx  (Bit x)                                          */
#define EXTI_IMR_Msk(x)                   (0x1UL<<EXTI_IMR_Pos(x))  /*!< IMRx  (Bitfield-Mask: 0x01)                            */
/* =========================================================  RECR  ========================================================== */
#define EXTI_RTSR_RTSR0_Pos               (0UL)                     /*!< RTSR0 (Bit 0)                                         */
#define EXTI_RTSR_RTSR0_Msk               (0x1UL)                   /*!< RTSR0 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTSR_RTSR1_Pos               (1UL)                     /*!< RTSR1 (Bit 1)                                         */
#define EXTI_RTSR_RTSR1_Msk               (0x2UL)                   /*!< RTSR1 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTSR_RTSR2_Pos               (2UL)                     /*!< RTSR2 (Bit 2)                                         */
#define EXTI_RTSR_RTSR2_Msk               (0x4UL)                   /*!< RTSR2 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTSR_RTSR3_Pos               (3UL)                     /*!< RTSR3 (Bit 3)                                         */
#define EXTI_RTSR_RTSR3_Msk               (0x8UL)                   /*!< RTSR3 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTSR_RTSR4_Pos               (4UL)                     /*!< RTSR4 (Bit 4)                                         */
#define EXTI_RTSR_RTSR4_Msk               (0x10UL)                  /*!< RTSR4 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTSR_RTSR5_Pos               (5UL)                     /*!< RTSR5 (Bit 5)                                         */
#define EXTI_RTSR_RTSR5_Msk               (0x20UL)                  /*!< RTSR5 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTSR_RTSR6_Pos               (6UL)                     /*!< RTSR6 (Bit 6)                                         */
#define EXTI_RTSR_RTSR6_Msk               (0x40UL)                  /*!< RTSR6 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTSR_RTSR7_Pos               (7UL)                     /*!< RTSR7 (Bit 7)                                         */
#define EXTI_RTSR_RTSR7_Msk               (0x80UL)                  /*!< RTSR7 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTSR_RTSR8_Pos               (8UL)                     /*!< RTSR8 (Bit 8)                                         */
#define EXTI_RTSR_RTSR8_Msk               (0x100UL)                 /*!< RTSR8 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTSR_RTSR9_Pos               (9UL)                     /*!< RTSR9 (Bit 9)                                         */
#define EXTI_RTSR_RTSR9_Msk               (0x200UL)                 /*!< RTSR9 (Bitfield-Mask: 0x01)                           */
#define EXTI_RTSR_RTSR10_Pos              (10UL)                    /*!< RTSR10 (Bit 10)                                       */
#define EXTI_RTSR_RTSR10_Msk              (0x400UL)                 /*!< RTSR10 (Bitfield-Mask: 0x01)                          */
#define EXTI_RTSR_RTSR11_Pos              (11UL)                    /*!< RTSR11 (Bit 11)                                       */
#define EXTI_RTSR_RTSR11_Msk              (0x800UL)                 /*!< RTSR11 (Bitfield-Mask: 0x01)                          */
#define EXTI_RTSR_RTSR12_Pos              (12UL)                    /*!< RTSR12 (Bit 12)                                       */
#define EXTI_RTSR_RTSR12_Msk              (0x1000UL)                /*!< RTSR12 (Bitfield-Mask: 0x01)                          */
#define EXTI_RTSR_RTSR13_Pos              (13UL)                    /*!< RTSR13 (Bit 13)                                       */
#define EXTI_RTSR_RTSR13_Msk              (0x2000UL)                /*!< RTSR13 (Bitfield-Mask: 0x01)                          */
#define EXTI_RTSR_RTSR14_Pos              (14UL)                    /*!< RTSR14 (Bit 14)                                       */
#define EXTI_RTSR_RTSR14_Msk              (0x4000UL)                /*!< RTSR14 (Bitfield-Mask: 0x01)                          */
#define EXTI_RTSR_RTSR15_Pos              (15UL)                    /*!< RTSR15 (Bit 15)                                       */
#define EXTI_RTSR_RTSR15_Msk              (0x8000UL)                /*!< RTSR15 (Bitfield-Mask: 0x01)                          */
#define EXTI_RTSR_Pos(x)                  ((uint32_t)x)             /*!< RTSRx  (Bit x)                                        */
#define EXTI_RTSR_Msk(x)                  (0x1UL<<EXTI_RTSR_Pos(x)) /*!< RTSRx  (Bitfield-Mask: 0x01)                          */
/* =========================================================  FECR  ========================================================== */
#define EXTI_FTSR_FTSR0_Pos               (0UL)                     /*!< FTSR0 (Bit 0)                                         */
#define EXTI_FTSR_FTSR0_Msk               (0x1UL)                   /*!< FTSR0 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTSR_FTSR1_Pos               (1UL)                     /*!< FTSR1 (Bit 1)                                         */
#define EXTI_FTSR_FTSR1_Msk               (0x2UL)                   /*!< FTSR1 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTSR_FTSR2_Pos               (2UL)                     /*!< FTSR2 (Bit 2)                                         */
#define EXTI_FTSR_FTSR2_Msk               (0x4UL)                   /*!< FTSR2 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTSR_FTSR3_Pos               (3UL)                     /*!< FTSR3 (Bit 3)                                         */
#define EXTI_FTSR_FTSR3_Msk               (0x8UL)                   /*!< FTSR3 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTSR_FTSR4_Pos               (4UL)                     /*!< FTSR4 (Bit 4)                                         */
#define EXTI_FTSR_FTSR4_Msk               (0x10UL)                  /*!< FTSR4 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTSR_FTSR5_Pos               (5UL)                     /*!< FTSR5 (Bit 5)                                         */
#define EXTI_FTSR_FTSR5_Msk               (0x20UL)                  /*!< FTSR5 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTSR_FTSR6_Pos               (6UL)                     /*!< FTSR6 (Bit 6)                                         */
#define EXTI_FTSR_FTSR6_Msk               (0x40UL)                  /*!< FTSR6 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTSR_FTSR7_Pos               (7UL)                     /*!< FTSR7 (Bit 7)                                         */
#define EXTI_FTSR_FTSR7_Msk               (0x80UL)                  /*!< FTSR7 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTSR_FTSR8_Pos               (8UL)                     /*!< FTSR8 (Bit 8)                                         */
#define EXTI_FTSR_FTSR8_Msk               (0x100UL)                 /*!< FTSR8 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTSR_FTSR9_Pos               (9UL)                     /*!< FTSR9 (Bit 9)                                         */
#define EXTI_FTSR_FTSR9_Msk               (0x200UL)                 /*!< FTSR9 (Bitfield-Mask: 0x01)                           */
#define EXTI_FTSR_FTSR10_Pos              (10UL)                    /*!< FTSR10 (Bit 10)                                       */
#define EXTI_FTSR_FTSR10_Msk              (0x400UL)                 /*!< FTSR10 (Bitfield-Mask: 0x01)                          */
#define EXTI_FTSR_FTSR11_Pos              (11UL)                    /*!< FTSR11 (Bit 11)                                       */
#define EXTI_FTSR_FTSR11_Msk              (0x800UL)                 /*!< FTSR11 (Bitfield-Mask: 0x01)                          */
#define EXTI_FTSR_FTSR12_Pos              (12UL)                    /*!< FTSR12 (Bit 12)                                       */
#define EXTI_FTSR_FTSR12_Msk              (0x1000UL)                /*!< FTSR12 (Bitfield-Mask: 0x01)                          */
#define EXTI_FTSR_FTSR13_Pos              (13UL)                    /*!< FTSR13 (Bit 13)                                       */
#define EXTI_FTSR_FTSR13_Msk              (0x2000UL)                /*!< FTSR13 (Bitfield-Mask: 0x01)                          */
#define EXTI_FTSR_FTSR14_Pos              (14UL)                    /*!< FTSR14 (Bit 14)                                       */
#define EXTI_FTSR_FTSR14_Msk              (0x4000UL)                /*!< FTSR14 (Bitfield-Mask: 0x01)                          */
#define EXTI_FTSR_FTSR15_Pos              (15UL)                    /*!< FTSR15 (Bit 15)                                       */
#define EXTI_FTSR_FTSR15_Msk              (0x8000UL)                /*!< FTSR15 (Bitfield-Mask: 0x01)                          */
#define EXTI_FTSR_Pos(x)                  ((uint32_t)x)             /*!< FTSRx  (Bit x)                                        */
#define EXTI_FTSR_Msk(x)                  (0x1UL<<EXTI_FTSR_Pos(x)) /*!< FTSRx  (Bitfield-Mask: 0x01)                          */
/* ========================================================  EXTICR   ======================================================== */
#define EXTI_EXTICR_EXTI0_Pos             (0UL)                     /*!< EXTI0 (Bit 0)                                         */
#define EXTI_EXTICR_EXTI0_Msk             (0xfUL)                   /*!< EXTI0 (Bitfield-Mask: 0x0f)                           */
#define EXTI_EXTICR_EXTI1_Pos             (4UL)                     /*!< EXTI1 (Bit 4)                                         */
#define EXTI_EXTICR_EXTI1_Msk             (0xf0UL)                  /*!< EXTI1 (Bitfield-Mask: 0x0f)                           */
#define EXTI_EXTICR_EXTI2_Pos             (8UL)                     /*!< EXTI2 (Bit 8)                                         */
#define EXTI_EXTICR_EXTI2_Msk             (0xf00UL)                 /*!< EXTI2 (Bitfield-Mask: 0x0f)                           */
#define EXTI_EXTICR_EXTI3_Pos             (12UL)                    /*!< EXTI3 (Bit 12)                                        */
#define EXTI_EXTICR_EXTI3_Msk             (0xf000UL)                /*!< EXTI3 (Bitfield-Mask: 0x0f)                           */
#define EXTI_EXTICR_Pos(x)                (4UL*((uint32_t)x%0x04UL))   /*!< EXTIx (Bit 4*x)                                    */
#define EXTI_EXTICR_Msk(x)                (0xfUL<<EXTI_EXTICR_Pos(x))  /*!< EXTIx (Bitfield-Mask: 0x0f)                        */


/* =========================================================================================================================== */
/* ================                                           CAN                                             ================ */
/* =========================================================================================================================== */

/* =======================================================  TBUF/RBUF  ======================================================= */
#define CAN_INFO_ID_Pos                   (0UL)                     /*!< IDE (Bit 0)                                           */
#define CAN_INFO_ID_Msk                   (0x1FFFFFFFUL)            /*!< IDE (Bitfield-Mask: 0x1FFFFFFF)                       */
#define CAN_INFO_ESI_Pos                  (31UL)                    /*!< IDE (Bit 31)                                          */
#define CAN_INFO_ESI_Msk                  (0x80000000UL)            /*!< IDE (Bitfield-Mask: 0x01)                             */
#define CAN_INFO_DLC_Pos                  (0UL)                     /*!< IDE (Bit 0)                                           */
#define CAN_INFO_DLC_Msk                  (0x0FUL)                  /*!< IDE (Bitfield-Mask: 0x0F)                             */
#define CAN_INFO_BRS_Pos                  (4UL)                     /*!< IDE (Bit 4)                                           */
#define CAN_INFO_BRS_Msk                  (0x10UL)                  /*!< IDE (Bitfield-Mask: 0x01)                             */
#define CAN_INFO_FDF_Pos                  (5UL)                     /*!< IDE (Bit 5)                                           */
#define CAN_INFO_FDF_Msk                  (0x20UL)                  /*!< IDE (Bitfield-Mask: 0x01)                             */
#define CAN_INFO_RTR_Pos                  (6UL)                     /*!< IDE (Bit 6)                                           */
#define CAN_INFO_RTR_Msk                  (0x40UL)                  /*!< IDE (Bitfield-Mask: 0x01)                             */
#define CAN_INFO_IDE_Pos                  (7UL)                     /*!< IDE (Bit 7)                                           */
#define CAN_INFO_IDE_Msk                  (0x80UL)                  /*!< IDE (Bitfield-Mask: 0x01)                             */
/* =========================================================  CTRL0  ========================================================= */
#define CAN_CTRL0_BUSOFF_Pos              (0UL)                     /*!< BUSOFF (Bit 0)                                        */
#define CAN_CTRL0_BUSOFF_Msk              (0x1UL)                   /*!< BUSOFF (Bitfield-Mask: 0x01)                          */
#define CAN_CTRL0_TACTIVE_Pos             (1UL)                     /*!< TACTIVE (Bit 1)                                       */
#define CAN_CTRL0_TACTIVE_Msk             (0x2UL)                   /*!< TACTIVE (Bitfield-Mask: 0x01)                         */
#define CAN_CTRL0_RACTIVE_Pos             (2UL)                     /*!< RACTIVE (Bit 2)                                       */
#define CAN_CTRL0_RACTIVE_Msk             (0x4UL)                   /*!< RACTIVE (Bitfield-Mask: 0x01)                         */
#define CAN_CTRL0_TSSS_Pos                (3UL)                     /*!< TSSS (Bit 3)                                          */
#define CAN_CTRL0_TSSS_Msk                (0x8UL)                   /*!< TSSS (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL0_TPSS_Pos                (4UL)                     /*!< TPSS (Bit 4)                                          */
#define CAN_CTRL0_TPSS_Msk                (0x10UL)                  /*!< TPSS (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL0_LBMI_Pos                (5UL)                     /*!< LBMI (Bit 5)                                          */
#define CAN_CTRL0_LBMI_Msk                (0x20UL)                  /*!< LBMI (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL0_LBME_Pos                (6UL)                     /*!< LBME (Bit 6)                                          */
#define CAN_CTRL0_LBME_Msk                (0x40UL)                  /*!< LBME (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL0_RESET_Pos               (7UL)                     /*!< RESET (Bit 7)                                         */
#define CAN_CTRL0_RESET_Msk               (0x80UL)                  /*!< RESET (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL0_TSA_Pos                 (8UL)                     /*!< TSA (Bit 8)                                           */
#define CAN_CTRL0_TSA_Msk                 (0x100UL)                 /*!< TSA (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL0_TSALL_Pos               (9UL)                     /*!< TSALL (Bit 9)                                         */
#define CAN_CTRL0_TSALL_Msk               (0x200UL)                 /*!< TSALL (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL0_TSONE_Pos               (10UL)                    /*!< TSONE (Bit 10)                                        */
#define CAN_CTRL0_TSONE_Msk               (0x400UL)                 /*!< TSONE (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL0_TPA_Pos                 (11UL)                    /*!< TPA (Bit 11)                                          */
#define CAN_CTRL0_TPA_Msk                 (0x800UL)                 /*!< TPA (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL0_TPE_Pos                 (12UL)                    /*!< TPE (Bit 12)                                          */
#define CAN_CTRL0_TPE_Msk                 (0x1000UL)                /*!< TPE (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL0_STBY_Pos                (13UL)                    /*!< STBY (Bit 13)                                         */
#define CAN_CTRL0_STBY_Msk                (0x2000UL)                /*!< STBY (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL0_LOM_Pos                 (14UL)                    /*!< LOM (Bit 14)                                          */
#define CAN_CTRL0_LOM_Msk                 (0x4000UL)                /*!< LOM (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL0_TBSEL_Pos               (15UL)                    /*!< TBSEL (Bit 15)                                        */
#define CAN_CTRL0_TBSEL_Msk               (0x8000UL)                /*!< TBSEL (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL0_TSSTAT_Pos              (16UL)                    /*!< TSSTAT (Bit 16)                                       */
#define CAN_CTRL0_TSSTAT_Msk              (0x30000UL)               /*!< TSSTAT (Bitfield-Mask: 0x03)                          */
#define CAN_CTRL0_TSMODE_Pos              (21UL)                    /*!< TSMODE (Bit 21)                                       */
#define CAN_CTRL0_TSMODE_Msk              (0x200000UL)              /*!< TSMODE (Bitfield-Mask: 0x01)                          */
#define CAN_CTRL0_TSNEXT_Pos              (22UL)                    /*!< TSNEXT (Bit 22)                                       */
#define CAN_CTRL0_TSNEXT_Msk              (0x400000UL)              /*!< TSNEXT (Bitfield-Mask: 0x01)                          */
#define CAN_CTRL0_FDISO_Pos               (23UL)                    /*!< FDISO (Bit 23)                                        */
#define CAN_CTRL0_FDISO_Msk               (0x800000UL)              /*!< FDISO (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL0_RSTAT_Pos               (24UL)                    /*!< RSTAT (Bit 24)                                        */
#define CAN_CTRL0_RSTAT_Msk               (0x3000000UL)             /*!< RSTAT (Bitfield-Mask: 0x03)                           */
#define CAN_CTRL0_RBALL_Pos               (27UL)                    /*!< RBALL (Bit 27)                                        */
#define CAN_CTRL0_RBALL_Msk               (0x8000000UL)             /*!< RBALL (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL0_RREL_Pos                (28UL)                    /*!< RREL (Bit 28)                                         */
#define CAN_CTRL0_RREL_Msk                (0x10000000UL)            /*!< RREL (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL0_ROV_Pos                 (29UL)                    /*!< ROV (Bit 29)                                          */
#define CAN_CTRL0_ROV_Msk                 (0x20000000UL)            /*!< ROV (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL0_ROM_Pos                 (30UL)                    /*!< ROM (Bit 30)                                          */
#define CAN_CTRL0_ROM_Msk                 (0x40000000UL)            /*!< ROM (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL0_SACK_Pos                (31UL)                    /*!< SACK (Bit 31)                                         */
#define CAN_CTRL0_SACK_Msk                (0x80000000UL)            /*!< SACK (Bitfield-Mask: 0x01)                            */
/* =========================================================  CTRL1  ========================================================= */
#define CAN_CTRL1_TSFF_Pos                (0UL)                     /*!< TSFF (Bit 0)                                          */
#define CAN_CTRL1_TSFF_Msk                (0x1UL)                   /*!< TSFF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_EIE_Pos                 (1UL)                     /*!< EIE (Bit 1)                                           */
#define CAN_CTRL1_EIE_Msk                 (0x2UL)                   /*!< EIE (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL1_TSIE_Pos                (2UL)                     /*!< TSIE (Bit 2)                                          */
#define CAN_CTRL1_TSIE_Msk                (0x4UL)                   /*!< TSIE (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_TPIE_Pos                (3UL)                     /*!< TPIE (Bit 3)                                          */
#define CAN_CTRL1_TPIE_Msk                (0x8UL)                   /*!< TPIE (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_RAFIE_Pos               (4UL)                     /*!< RAFIE (Bit 4)                                         */
#define CAN_CTRL1_RAFIE_Msk               (0x10UL)                  /*!< RAFIE (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL1_RFIE_Pos                (5UL)                     /*!< RFIE (Bit 5)                                          */
#define CAN_CTRL1_RFIE_Msk                (0x20UL)                  /*!< RFIE (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_ROIE_Pos                (6UL)                     /*!< ROIE (Bit 6)                                          */
#define CAN_CTRL1_ROIE_Msk                (0x40UL)                  /*!< ROIE (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_RIE_Pos                 (7UL)                     /*!< RIE (Bit 7)                                           */
#define CAN_CTRL1_RIE_Msk                 (0x80UL)                  /*!< RIE (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL1_AIF_Pos                 (8UL)                     /*!< AIF (Bit 8)                                           */
#define CAN_CTRL1_AIF_Msk                 (0x100UL)                 /*!< AIF (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL1_EIF_Pos                 (9UL)                     /*!< EIF (Bit 9)                                           */
#define CAN_CTRL1_EIF_Msk                 (0x200UL)                 /*!< EIF (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL1_TSIF_Pos                (10UL)                    /*!< TSIF (Bit 10)                                         */
#define CAN_CTRL1_TSIF_Msk                (0x400UL)                 /*!< TSIF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_TPIF_Pos                (11UL)                    /*!< TPIF (Bit 11)                                         */
#define CAN_CTRL1_TPIF_Msk                (0x800UL)                 /*!< TPIF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_RAFIF_Pos               (12UL)                    /*!< RAFIF (Bit 12)                                        */
#define CAN_CTRL1_RAFIF_Msk               (0x1000UL)                /*!< RAFIF (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL1_RFIF_Pos                (13UL)                    /*!< RFIF (Bit 13)                                         */
#define CAN_CTRL1_RFIF_Msk                (0x2000UL)                /*!< RFIF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_ROIF_Pos                (14UL)                    /*!< ROIF (Bit 14)                                         */
#define CAN_CTRL1_ROIF_Msk                (0x4000UL)                /*!< ROIF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_RIF_Pos                 (15UL)                    /*!< RIF (Bit 15)                                          */
#define CAN_CTRL1_RIF_Msk                 (0x8000UL)                /*!< RIF (Bitfield-Mask: 0x01)                             */
#define CAN_CTRL1_BEIF_Pos                (16UL)                    /*!< BEIF (Bit 16)                                         */
#define CAN_CTRL1_BEIF_Msk                (0x10000UL)               /*!< BEIF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_BEIE_Pos                (17UL)                    /*!< BEIE (Bit 17)                                         */
#define CAN_CTRL1_BEIE_Msk                (0x20000UL)               /*!< BEIE (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_ALIF_Pos                (18UL)                    /*!< ALIF (Bit 18)                                         */
#define CAN_CTRL1_ALIF_Msk                (0x40000UL)               /*!< ALIF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_ALIE_Pos                (19UL)                    /*!< ALIE (Bit 19)                                         */
#define CAN_CTRL1_ALIE_Msk                (0x80000UL)               /*!< ALIE (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_EPIF_Pos                (20UL)                    /*!< EPIF (Bit 20)                                         */
#define CAN_CTRL1_EPIF_Msk                (0x100000UL)              /*!< EPIF (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_EPIE_Pos                (21UL)                    /*!< EPIE (Bit 21)                                         */
#define CAN_CTRL1_EPIE_Msk                (0x200000UL)              /*!< EPIE (Bitfield-Mask: 0x01)                            */
#define CAN_CTRL1_EPASS_Pos               (22UL)                    /*!< EPASS (Bit 22)                                        */
#define CAN_CTRL1_EPASS_Msk               (0x400000UL)              /*!< EPASS (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL1_EWARN_Pos               (23UL)                    /*!< EWARN (Bit 23)                                        */
#define CAN_CTRL1_EWARN_Msk               (0x800000UL)              /*!< EWARN (Bitfield-Mask: 0x01)                           */
#define CAN_CTRL1_EWL_Pos                 (24UL)                    /*!< EWL (Bit 24)                                          */
#define CAN_CTRL1_EWL_Msk                 (0xf000000UL)             /*!< EWL (Bitfield-Mask: 0x0f)                             */
#define CAN_CTRL1_AFWL_Pos                (28UL)                    /*!< AFWL (Bit 28)                                         */
#define CAN_CTRL1_AFWL_Msk                (0xf0000000UL)            /*!< AFWL (Bitfield-Mask: 0x0f)                            */
/* =======================================================  SBITRATE  ======================================================== */
#define CAN_BITRATE_SEG_1_Pos             (0UL)                     /*!< SEG_1 (Bit 0)                                         */
#define CAN_BITRATE_SEG_1_Msk             (0xffUL)                  /*!< SEG_1 (Bitfield-Mask: 0xff)                           */
#define CAN_BITRATE_SEG_2_Pos             (8UL)                     /*!< SEG_2 (Bit 8)                                         */
#define CAN_BITRATE_SEG_2_Msk             (0x7f00UL)                /*!< SEG_2 (Bitfield-Mask: 0x7f)                           */
#define CAN_BITRATE_SJW_Pos               (16UL)                    /*!< SJW (Bit 16)                                          */
#define CAN_BITRATE_SJW_Msk               (0x7f0000UL)              /*!< SJW (Bitfield-Mask: 0x7f)                             */
#define CAN_BITRATE_PRESC_Pos             (24UL)                    /*!< PRESC (Bit 24)                                        */
#define CAN_BITRATE_PRESC_Msk             (0xff000000UL)            /*!< PRESC (Bitfield-Mask: 0xff)                           */
/* ========================================================  ERRINFO  ======================================================== */
#define CAN_ERRINFO_ALC_Pos               (0UL)                     /*!< ALC (Bit 0)                                           */
#define CAN_ERRINFO_ALC_Msk               (0x1fUL)                  /*!< ALC (Bitfield-Mask: 0x1f)                             */
#define CAN_ERRINFO_KOER_Pos              (5UL)                     /*!< KOER (Bit 5)                                          */
#define CAN_ERRINFO_KOER_Msk              (0xe0UL)                  /*!< KOER (Bitfield-Mask: 0x07)                            */
#define CAN_ERRINFO_SSPOFF_Pos            (8UL)                     /*!< SSPOFF (Bit 8)                                        */
#define CAN_ERRINFO_SSPOFF_Msk            (0x7f00UL)                /*!< SSPOFF (Bitfield-Mask: 0x7f)                          */
#define CAN_ERRINFO_TDCEN_Pos             (15UL)                    /*!< TDCEN (Bit 15)                                        */
#define CAN_ERRINFO_TDCEN_Msk             (0x8000UL)                /*!< TDCEN (Bitfield-Mask: 0x01)                           */
#define CAN_ERRINFO_RECNT_Pos             (16UL)                    /*!< RECNT (Bit 16)                                        */
#define CAN_ERRINFO_RECNT_Msk             (0xff0000UL)              /*!< RECNT (Bitfield-Mask: 0xff)                           */
#define CAN_ERRINFO_TECNT_Pos             (24UL)                    /*!< TECNT (Bit 24)                                        */
#define CAN_ERRINFO_TECNT_Msk             (0xff000000UL)            /*!< TECNT (Bitfield-Mask: 0xff)                           */
/* ========================================================  ACFCTRL  ======================================================== */
#define CAN_ACFCTRL_ACFADR_Pos            (0UL)                     /*!< ACFADR (Bit 0)                                        */
#define CAN_ACFCTRL_ACFADR_Msk            (0xfUL)                   /*!< ACFADR (Bitfield-Mask: 0x0f)                          */
#define CAN_ACFCTRL_SELMASK_Pos           (5UL)                     /*!< SELMASK (Bit 5)                                       */
#define CAN_ACFCTRL_SELMASK_Msk           (0x20UL)                  /*!< SELMASK (Bitfield-Mask: 0x01)                         */
#define CAN_ACFCTRL_TIMEEN_Pos            (8UL)                     /*!< TIMEEN (Bit 8)                                        */
#define CAN_ACFCTRL_TIMEEN_Msk            (0x100UL)                 /*!< TIMEEN (Bitfield-Mask: 0x01)                          */
#define CAN_ACFCTRL_TIMEPOS_Pos           (9UL)                     /*!< TIMEPOS (Bit 9)                                       */
#define CAN_ACFCTRL_TIMEPOS_Msk           (0x200UL)                 /*!< TIMEPOS (Bitfield-Mask: 0x01)                         */
#define CAN_ACFCTRL_ACFEN_Pos             (16UL)                    /*!< ACFEN (Bit 16)                                        */
#define CAN_ACFCTRL_ACFEN_Msk             (0xffff0000UL)            /*!< ACFEN (Bitfield-Mask: 0xffff)                         */
/* ==========================================================  ACF  ========================================================== */
#define CAN_ACF_ACODE_Pos                 (0UL)                     /*!< ACODE (Bit 0)                                         */
#define CAN_ACF_ACODE_Msk                 (0x1fffffffUL)            /*!< ACODE (Bitfield-Mask: 0x1fffffff)                     */
#define CAN_ACF_AIDE_Pos                  (29UL)                    /*!< AIDE (Bit 29)                                         */
#define CAN_ACF_AIDE_Msk                  (0x20000000UL)            /*!< AIDE (Bitfield-Mask: 0x01)                            */
#define CAN_ACF_AIDEE_Pos                 (30UL)                    /*!< AIDEE (Bit 30)                                        */
#define CAN_ACF_AIDEE_Msk                 (0x40000000UL)            /*!< AIDEE (Bitfield-Mask: 0x01)                           */
/* ========================================================  VERTION  ======================================================== */
#define CAN_VERSION_VERSION_Pos           (0UL)                     /*!< VERSION (Bit 0)                                       */
#define CAN_VERSION_VERSION_Msk           (0xffffUL)                /*!< VERSION (Bitfield-Mask: 0xffff)                       */


/* =========================================================================================================================== */
/* ================                                           UART                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  RBR  ========================================================== */
#define UART_RBR_RBR_THR_Pos              (0UL)                     /*!< RBR_THR (Bit 0)                                       */
#define UART_RBR_RBR_THR_Msk              (0x1ffUL)                 /*!< RBR_THR (Bitfield-Mask: 0x1ff)                        */
/* =========================================================  DIV_L  ========================================================= */
#define UART_DIV_L_DIV_L_Pos              (0UL)                     /*!< DIV_L (Bit 0)                                         */
#define UART_DIV_L_DIV_L_Msk              (0xffUL)                  /*!< DIV_L (Bitfield-Mask: 0xff)                           */
/* =========================================================  DIV_H  ========================================================= */
#define UART_DIV_H_DIV_H_Pos              (0UL)                     /*!< DIV_H (Bit 0)                                         */
#define UART_DIV_H_DIV_H_Msk              (0xffUL)                  /*!< DIV_H (Bitfield-Mask: 0xff)                           */
/* =========================================================  LCR0  ========================================================== */
#define UART_LCR0_WLS1_WLS0_Pos          (0UL)                      /*!< WLS1_WLS0 (Bit 0)                                     */
#define UART_LCR0_WLS1_WLS0_Msk          (0x3UL)                    /*!< WLS1_WLS0 (Bitfield-Mask: 0x03)                       */
#define UART_LCR0_STB_Pos                 (2UL)                     /*!< STB (Bit 2)                                           */
#define UART_LCR0_STB_Msk                 (0x4UL)                   /*!< STB (Bitfield-Mask: 0x01)                             */
#define UART_LCR0_PEN_Pos                 (3UL)                     /*!< PEN (Bit 3)                                           */
#define UART_LCR0_PEN_Msk                 (0x8UL)                   /*!< PEN (Bitfield-Mask: 0x01)                             */
#define UART_LCR0_EPS_Pos                 (4UL)                     /*!< EPS (Bit 4)                                           */
#define UART_LCR0_EPS_Msk                 (0x10UL)                  /*!< EPS (Bitfield-Mask: 0x01)                             */
#define UART_LCR0_SP_Pos                  (5UL)                     /*!< SP (Bit 5)                                            */
#define UART_LCR0_SP_Msk                  (0x20UL)                  /*!< SP (Bitfield-Mask: 0x01)                              */
#define UART_LCR0_SUB_Pos                 (6UL)                     /*!< SUB (Bit 6)                                           */
#define UART_LCR0_SUB_Msk                 (0x40UL)                  /*!< SUB (Bitfield-Mask: 0x01)                             */
/* =========================================================  LCR1  ========================================================== */
#define UART_LCR1_RXEN_Pos                (0UL)                     /*!< RXEN (Bit 0)                                          */
#define UART_LCR1_RXEN_Msk                (0x1UL)                   /*!< RXEN (Bitfield-Mask: 0x01)                            */
#define UART_LCR1_TXEN_Pos                (1UL)                     /*!< TXEN (Bit 1)                                          */
#define UART_LCR1_TXEN_Msk                (0x2UL)                   /*!< TXEN (Bitfield-Mask: 0x01)                            */
#define UART_LCR1_LOOP_Pos                (4UL)                     /*!< LOOP (Bit 4)                                          */
#define UART_LCR1_LOOP_Msk                (0x10UL)                  /*!< LOOP (Bitfield-Mask: 0x01)                            */
#define UART_LCR1_WLS2_Pos                (5UL)                     /*!< WLS2 (Bit 5)                                          */
#define UART_LCR1_WLS2_Msk                (0x20UL)                  /*!< WLS2 (Bitfield-Mask: 0x01)                            */
#define UART_LCR1_INVRX_Pos               (6UL)                     /*!< INVRX (Bit 6)                                         */
#define UART_LCR1_INVRX_Msk               (0x40UL)                  /*!< INVRX (Bitfield-Mask: 0x01)                           */
#define UART_LCR1_INVTX_Pos               (7UL)                     /*!< INVTX (Bit 7)                                         */
#define UART_LCR1_INVTX_Msk               (0x80UL)                  /*!< INVTX (Bitfield-Mask: 0x01)                           */
/* ==========================================================  FCR  ========================================================== */
#define UART_FCR_FIFOE_Pos                (0UL)                     /*!< FIFOE (Bit 0)                                         */
#define UART_FCR_FIFOE_Msk                (0x1UL)                   /*!< FIFOE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  EFR  ========================================================== */
#define UART_EFR_RTS_Pos                  (6UL)                     /*!< RTS (Bit 6)                                           */
#define UART_EFR_RTS_Msk                  (0x40UL)                  /*!< RTS (Bitfield-Mask: 0x01)                             */
#define UART_EFR_CTS_Pos                  (7UL)                     /*!< CTS (Bit 7)                                           */
#define UART_EFR_CTS_Msk                  (0x80UL)                  /*!< CTS (Bitfield-Mask: 0x01)                             */
/* ==========================================================  IER  ========================================================== */
#define UART_IER_ERXNE_Pos                (0UL)                     /*!< ERXNE (Bit 0)                                         */
#define UART_IER_ERXNE_Msk                (0x1UL)                   /*!< ERXNE (Bitfield-Mask: 0x01)                           */
#define UART_IER_ETXE_Pos                 (1UL)                     /*!< ETXE (Bit 1)                                          */
#define UART_IER_ETXE_Msk                 (0x2UL)                   /*!< ETXE (Bitfield-Mask: 0x01)                            */
#define UART_IER_ETC_Pos                  (2UL)                     /*!< ETC (Bit 2)                                           */
#define UART_IER_ETC_Msk                  (0x4UL)                   /*!< ETC (Bitfield-Mask: 0x01)                             */
#define UART_IER_EPE_Pos                  (3UL)                     /*!< EPE (Bit 3)                                           */
#define UART_IER_EPE_Msk                  (0x8UL)                   /*!< EPE (Bitfield-Mask: 0x01)                             */
#define UART_IER_EFE_Pos                  (4UL)                     /*!< EFE (Bit 4)                                           */
#define UART_IER_EFE_Msk                  (0x10UL)                  /*!< EFE (Bitfield-Mask: 0x01)                             */
#define UART_IER_ENE_Pos                  (5UL)                     /*!< ENE (Bit 5)                                           */
#define UART_IER_ENE_Msk                  (0x20UL)                  /*!< ENE (Bitfield-Mask: 0x01)                             */
#define UART_IER_EOEBI_Pos                (6UL)                     /*!< EOEBI (Bit 6)                                         */
#define UART_IER_EOEBI_Msk                (0x40UL)                  /*!< EOEBI (Bitfield-Mask: 0x01)                           */
#define UART_IER_EDCTS_Pos                (7UL)                     /*!< EDCTS (Bit 7)                                         */
#define UART_IER_EDCTS_Msk                (0x80UL)                  /*!< EDCTS (Bitfield-Mask: 0x01)                           */
#define UART_IER_ETXDF_Pos                (8UL)                     /*!< ETXDF (Bit 8)                                         */
#define UART_IER_ETXDF_Msk                (0x100UL)                 /*!< ETXDF (Bitfield-Mask: 0x01)                           */
/* =========================================================  LSR0  ========================================================== */
#define UART_LSR0_DR_Pos                  (0UL)                     /*!< DR (Bit 0)                                            */
#define UART_LSR0_DR_Msk                  (0x1UL)                   /*!< DR (Bitfield-Mask: 0x01)                              */
#define UART_LSR0_OE_Pos                  (1UL)                     /*!< OE (Bit 1)                                            */
#define UART_LSR0_OE_Msk                  (0x2UL)                   /*!< OE (Bitfield-Mask: 0x01)                              */
#define UART_LSR0_PE_Pos                  (2UL)                     /*!< PE (Bit 2)                                            */
#define UART_LSR0_PE_Msk                  (0x4UL)                   /*!< PE (Bitfield-Mask: 0x01)                              */
#define UART_LSR0_FE_Pos                  (3UL)                     /*!< FE (Bit 3)                                            */
#define UART_LSR0_FE_Msk                  (0x8UL)                   /*!< FE (Bitfield-Mask: 0x01)                              */
#define UART_LSR0_BI_Pos                  (4UL)                     /*!< BI (Bit 4)                                            */
#define UART_LSR0_BI_Msk                  (0x10UL)                  /*!< BI (Bitfield-Mask: 0x01)                              */
#define UART_LSR0_THRE_Pos                (5UL)                     /*!< THRE (Bit 5)                                          */
#define UART_LSR0_THRE_Msk                (0x20UL)                  /*!< THRE (Bitfield-Mask: 0x01)                            */
#define UART_LSR0_TC_Pos                  (6UL)                     /*!< TC (Bit 6)                                            */
#define UART_LSR0_TC_Msk                  (0x40UL)                  /*!< TC (Bitfield-Mask: 0x01)                              */
#define UART_LSR0_NE_Pos                  (7UL)                     /*!< NE (Bit 7)                                            */
#define UART_LSR0_NE_Msk                  (0x80UL)                  /*!< NE (Bitfield-Mask: 0x01)                              */
#define UART_LSR0_TXDF_Pos                (8UL)                     /*!< TXDF (Bit 8)                                          */
#define UART_LSR0_TXDF_Msk                (0x100UL)                 /*!< TXDF (Bitfield-Mask: 0x01)                            */
/* =========================================================  LSR1  ========================================================== */
#define UART_LSR1_IDLE_Pos                (0UL)                     /*!< IDLE (Bit 0)                                          */
#define UART_LSR1_IDLE_Msk                (0x1UL)                   /*!< IDLE (Bitfield-Mask: 0x01)                            */
#define UART_LSR1_SYNERR_Pos              (1UL)                     /*!< SYNERR (Bit 1)                                        */
#define UART_LSR1_SYNERR_Msk              (0x2UL)                   /*!< SYNERR (Bitfield-Mask: 0x01)                            */
#define UART_LSR1_FBRK_Pos                (2UL)                     /*!< FBRK (Bit 2)                                          */
#define UART_LSR1_FBRK_Msk                (0x4UL)                   /*!< FBRK (Bitfield-Mask: 0x01)                            */
#define UART_LSR1_DCTS_Pos                (3UL)                     /*!< DCTS (Bit 3)                                          */
#define UART_LSR1_DCTS_Msk                (0x8UL)                   /*!< DCTS (Bitfield-Mask: 0x01)                            */
#define UART_LSR1_BRKWAK_Pos              (4UL)                     /*!< BRKWAK (Bit 4)                                        */
#define UART_LSR1_BRKWAK_Msk              (0x10UL)                  /*!< BRKWAK (Bitfield-Mask: 0x01)                          */
#define UART_LSR1_UART_IDLE_Pos           (5UL)                     /*!< UART_IDLE (Bit 5)                                     */
#define UART_LSR1_UART_IDLE_Msk           (0x20UL)                  /*!< UART_IDLE (Bitfield-Mask: 0x01)                       */
#define UART_LSR1_CTS_Pos                 (6UL)                     /*!< CTS (Bit 6)                                           */
#define UART_LSR1_CTS_Msk                 (0x40UL)                  /*!< CTS (Bitfield-Mask: 0x01)                             */
#define UART_LSR1_RTS_Pos                 (7UL)                     /*!< RTS (Bit 7)                                           */
#define UART_LSR1_RTS_Msk                 (0x80UL)                  /*!< RTS (Bitfield-Mask: 0x01)                             */
/* ========================================================  SMP_CNT  ======================================================== */
#define UART_SMP_CNT_SMP_CNT_Pos          (0UL)                     /*!< SMP_CNT (Bit 0)                                       */
#define UART_SMP_CNT_SMP_CNT_Msk          (0x3UL)                   /*!< SMP_CNT (Bitfield-Mask: 0x03)                         */
/* =========================================================  GUARD  ========================================================= */
#define UART_GUARD_GUARD_CNT_Pos          (0UL)                     /*!< GUARD_CNT (Bit 0)                                     */
#define UART_GUARD_GUARD_CNT_Msk          (0xfUL)                   /*!< GUARD_CNT (Bitfield-Mask: 0x0f)                       */
#define UART_GUARD_GUARD_EN_Pos           (4UL)                     /*!< GUARD_EN (Bit 4)                                      */
#define UART_GUARD_GUARD_EN_Msk           (0x10UL)                  /*!< GUARD_EN (Bitfield-Mask: 0x01)                        */
/* =======================================================  SLEEP_EN  ======================================================== */
#define UART_SLEEP_EN_SLEEP_EN_Pos        (0UL)                     /*!< SLEEP_EN (Bit 0)                                      */
#define UART_SLEEP_EN_SLEEP_EN_Msk        (0x1UL)                   /*!< SLEEP_EN (Bitfield-Mask: 0x01)                        */
/* ========================================================  DMA_EN  ========================================================= */
#define UART_DMA_EN_RX_DMA_EN_Pos        (0UL)                      /*!< RX_DMA_EN (Bit 0)                                     */
#define UART_DMA_EN_RX_DMA_EN_Msk        (0x1UL)                    /*!< RX_DMA_EN (Bitfield-Mask: 0x01)                       */
#define UART_DMA_EN_TX_DMA_EN_Pos        (1UL)                      /*!< TX_DMA_EN (Bit 1)                                     */
#define UART_DMA_EN_TX_DMA_EN_Msk        (0x2UL)                    /*!< TX_DMA_EN (Bitfield-Mask: 0x01)                       */
/* =======================================================  DIV_FRAC  ======================================================== */
#define UART_DIV_FRAC_DIV_FRAC_Pos        (0UL)                     /*!< DIV_FRAC (Bit 0)                                      */
#define UART_DIV_FRAC_DIV_FRAC_Msk        (0xffUL)                  /*!< DIV_FRAC (Bitfield-Mask: 0xff)                        */
/* ========================================================  RS485CR  ======================================================== */
#define UART_RS485CR_DLYEN_Pos            (4UL)                     /*!< DLYEN (Bit 4)                                         */
#define UART_RS485CR_DLYEN_Msk            (0x10UL)                  /*!< DLYEN (Bitfield-Mask: 0x01)                           */
#define UART_RS485CR_INVPOL_Pos           (5UL)                     /*!< INVPOL (Bit 5)                                        */
#define UART_RS485CR_INVPOL_Msk           (0x20UL)                  /*!< INVPOL (Bitfield-Mask: 0x01)                          */
#define UART_RS485CR_RS485EN_Pos          (7UL)                     /*!< RS485EN (Bit 7)                                       */
#define UART_RS485CR_RS485EN_Msk          (0x80UL)                  /*!< RS485EN (Bitfield-Mask: 0x01)                         */
/* =========================================================  CNTR  ========================================================== */
#define UART_CNTR_CNTR_Pos                (0UL)                     /*!< CNTR (Bit 0)                                          */
#define UART_CNTR_CNTR_Msk                (0xffUL)                  /*!< CNTR (Bitfield-Mask: 0xff)                            */
/* =========================================================  IDLE  ========================================================== */
#define UART_IDLE_IDLEIE_Pos              (4UL)                     /*!< IDLEIE (Bit 4)                                        */
#define UART_IDLE_IDLEIE_Msk              (0x10UL)                  /*!< IDLEIE (Bitfield-Mask: 0x01)                          */
#define UART_IDLE_ILEN_Pos                (7UL)                     /*!< ILEN (Bit 7)                                          */
#define UART_IDLE_ILEN_Msk                (0x80UL)                  /*!< ILEN (Bitfield-Mask: 0x01)                            */
/* =========================================================  LINCR  ========================================================= */
#define UART_LINCR_BRKWAKIE_Pos           (1UL)                     /*!< BRKWAKIE (Bit 1)                                      */
#define UART_LINCR_BRKWAKIE_Msk           (0x2UL)                   /*!< BRKWAKIE (Bitfield-Mask: 0x01)                        */
#define UART_LINCR_SYNERRIE_Pos           (2UL)                     /*!< SYNERRIE (Bit 2)                                      */
#define UART_LINCR_SYNERRIE_Msk           (0x4UL)                   /*!< SYNERRIE (Bitfield-Mask: 0x01)                        */
#define UART_LINCR_LABAUDEN_Pos           (3UL)                     /*!< LABAUDEN (Bit 3)                                      */
#define UART_LINCR_LABAUDEN_Msk           (0x8UL)                   /*!< LABAUDEN (Bitfield-Mask: 0x01)                        */
#define UART_LINCR_SDBRK_Pos              (4UL)                     /*!< SDBRK (Bit 4)                                         */
#define UART_LINCR_SDBRK_Msk              (0x10UL)                  /*!< SDBRK (Bitfield-Mask: 0x01)                           */
#define UART_LINCR_LBRKDL_Pos             (5UL)                     /*!< LBRKDL (Bit 5)                                        */
#define UART_LINCR_LBRKDL_Msk             (0x20UL)                  /*!< LBRKDL (Bitfield-Mask: 0x01)                          */
#define UART_LINCR_LBRKIE_Pos             (6UL)                     /*!< LBRKIE (Bit 6)                                        */
#define UART_LINCR_LBRKIE_Msk             (0x40UL)                  /*!< LBRKIE (Bitfield-Mask: 0x01)                          */
#define UART_LINCR_LINEN_Pos              (7UL)                     /*!< LINEN (Bit 7)                                         */
#define UART_LINCR_LINEN_Msk              (0x80UL)                  /*!< LINEN (Bitfield-Mask: 0x01)                           */
/* =========================================================  BRKLGH  ========================================================= */
#define UART_BRKLGH_BRKLGH_Pos             (0UL)                    /*!< BRKLGH (Bit 0)                                        */
#define UART_BRKLGH_BRKLGH_Msk             (0xfUL)                  /*!< BRKLGH (Bitfield-Mask: 0x0f)                          */


/* =========================================================================================================================== */
/* ================                                           I2C                                             ================ */
/* =========================================================================================================================== */

/* =========================================================  ADDR0  ========================================================= */
#define I2C_ADDR0_AD_Pos                  (1UL)                     /*!< AD (Bit 1)                                            */
#define I2C_ADDR0_AD_Msk                  (0xfeUL)                  /*!< AD (Bitfield-Mask: 0x7f)                              */
/* =========================================================  ADDR1  ========================================================= */
#define I2C_ADDR1_AD_Pos                  (0UL)                     /*!< AD (Bit 0)                                            */
#define I2C_ADDR1_AD_Msk                  (0x7UL)                   /*!< AD (Bitfield-Mask: 0x07)                              */
#define I2C_ADDR1_RAD_Pos                 (4UL)                     /*!< RAD (Bit 4)                                           */
#define I2C_ADDR1_RAD_Msk                 (0x7f0UL)                 /*!< RAD (Bitfield-Mask: 0x7f)                             */
#define I2C_ADDR1_RMEN_Pos                (12UL)                    /*!< RMEN (Bit 12)                                         */
#define I2C_ADDR1_RMEN_Msk                (0x1000UL)                /*!< RMEN (Bitfield-Mask: 0x01)                            */
/* ======================================================  SAMPLE_CNT  ======================================================= */
#define I2C_SAMPLE_CNT_SAMPLE_CNT_Pos     (0UL)                     /*!< SAMPLE_CNT (Bit 0)                                    */
#define I2C_SAMPLE_CNT_SAMPLE_CNT_Msk     (0xffUL)                  /*!< SAMPLE_CNT (Bitfield-Mask: 0xff)                      */
/* =======================================================  STEP_CNT  ======================================================== */
#define I2C_STEP_CNT_STEP_CNT_Pos         (0UL)                     /*!< STEP_CNT (Bit 0)                                      */
#define I2C_STEP_CNT_STEP_CNT_Msk         (0xffUL)                  /*!< STEP_CNT (Bitfield-Mask: 0xff)                        */
/* =========================================================  CTRL0  ========================================================= */
#define I2C_CTRL0_WUEN_Pos                (2UL)                     /*!< WUEN (Bit 2)                                          */
#define I2C_CTRL0_WUEN_Msk                (0x4UL)                   /*!< WUEN (Bitfield-Mask: 0x01)                            */
#define I2C_CTRL0_TACK_Pos                (3UL)                     /*!< TACK (Bit 3)                                          */
#define I2C_CTRL0_TACK_Msk                (0x8UL)                   /*!< TACK (Bitfield-Mask: 0x01)                            */
#define I2C_CTRL0_TX_Pos                  (4UL)                     /*!< TX (Bit 4)                                            */
#define I2C_CTRL0_TX_Msk                  (0x10UL)                  /*!< TX (Bitfield-Mask: 0x01)                              */
#define I2C_CTRL0_MSTR_Pos                (5UL)                     /*!< MSTR (Bit 5)                                          */
#define I2C_CTRL0_MSTR_Msk                (0x20UL)                  /*!< MSTR (Bitfield-Mask: 0x01)                            */
#define I2C_CTRL0_IICIE_Pos               (6UL)                     /*!< IICIE (Bit 6)                                         */
#define I2C_CTRL0_IICIE_Msk               (0x40UL)                  /*!< IICIE (Bitfield-Mask: 0x01)                           */
#define I2C_CTRL0_IICEN_Pos               (7UL)                     /*!< IICEN (Bit 7)                                         */
#define I2C_CTRL0_IICEN_Msk               (0x80UL)                  /*!< IICEN (Bitfield-Mask: 0x01)                           */
/* =========================================================  CTRL1  ========================================================= */
#define I2C_CTRL1_STREN_Pos               (0UL)                     /*!< STREN (Bit 0)                                         */
#define I2C_CTRL1_STREN_Msk               (0x1UL)                   /*!< STREN (Bitfield-Mask: 0x01)                           */
#define I2C_CTRL1_ARBEN_Pos               (3UL)                     /*!< ARBEN (Bit 3)                                         */
#define I2C_CTRL1_ARBEN_Msk               (0x8UL)                   /*!< ARBEN (Bitfield-Mask: 0x01)                           */
#define I2C_CTRL1_SYNCEN_Pos              (4UL)                     /*!< SYNCEN (Bit 4)                                        */
#define I2C_CTRL1_SYNCEN_Msk              (0x10UL)                  /*!< SYNCEN (Bitfield-Mask: 0x01)                          */
#define I2C_CTRL1_ADEXT_Pos               (6UL)                     /*!< ADEXT (Bit 6)                                         */
#define I2C_CTRL1_ADEXT_Msk               (0x40UL)                  /*!< ADEXT (Bitfield-Mask: 0x01)                           */
#define I2C_CTRL1_GCAEN_Pos               (7UL)                     /*!< GCAEN (Bit 7)                                         */
#define I2C_CTRL1_GCAEN_Msk               (0x80UL)                  /*!< GCAEN (Bitfield-Mask: 0x01)                           */
/* =========================================================  CTRL2  ========================================================= */
#define I2C_CTRL2_MNTEN_Pos               (0UL)                     /*!< MNTEN (Bit 0)                                         */
#define I2C_CTRL2_MNTEN_Msk               (0x1UL)                   /*!< MNTEN (Bitfield-Mask: 0x01)                           */
#define I2C_CTRL2_NACKIE_Pos              (1UL)                     /*!< NACKIE (Bit 1)                                        */
#define I2C_CTRL2_NACKIE_Msk              (0x2UL)                   /*!< NACKIE (Bitfield-Mask: 0x01)                          */
#define I2C_CTRL2_TXEMIE_Pos              (4UL)                     /*!< TXEMIE (Bit 4)                                        */
#define I2C_CTRL2_TXEMIE_Msk              (0x10UL)                  /*!< TXEMIE (Bitfield-Mask: 0x01)                          */
#define I2C_CTRL2_RXFIE_Pos               (5UL)                     /*!< RXFIE (Bit 5)                                         */
#define I2C_CTRL2_RXFIE_Msk               (0x20UL)                  /*!< RXFIE (Bitfield-Mask: 0x01)                           */
#define I2C_CTRL2_TXUFIE_Pos              (6UL)                     /*!< TXUFIE (Bit 6)                                        */
#define I2C_CTRL2_TXUFIE_Msk              (0x40UL)                  /*!< TXUFIE (Bitfield-Mask: 0x01)                          */
#define I2C_CTRL2_RXOFIE_Pos              (7UL)                     /*!< RXOFIE (Bit 7)                                        */
#define I2C_CTRL2_RXOFIE_Msk              (0x80UL)                  /*!< RXOFIE (Bitfield-Mask: 0x01)                          */
/* =========================================================  CTRL3  ========================================================= */
#define I2C_CTRL3_DMATXEN_Pos             (0UL)                     /*!< DMATXEN (Bit 0)                                       */
#define I2C_CTRL3_DMATXEN_Msk             (0x1UL)                   /*!< DMATXEN (Bitfield-Mask: 0x01)                         */
#define I2C_CTRL3_DMARXEN_Pos             (1UL)                     /*!< DMARXEN (Bit 1)                                       */
#define I2C_CTRL3_DMARXEN_Msk             (0x2UL)                   /*!< DMARXEN (Bitfield-Mask: 0x01)                         */
/* ========================================================  STATUS0  ======================================================== */
#define I2C_STATUS0_RACK_Pos              (0UL)                     /*!< RACK (Bit 0)                                          */
#define I2C_STATUS0_RACK_Msk              (0x1UL)                   /*!< RACK (Bitfield-Mask: 0x01)                            */
#define I2C_STATUS0_SRW_Pos               (2UL)                     /*!< SRW (Bit 2)                                           */
#define I2C_STATUS0_SRW_Msk               (0x4UL)                   /*!< SRW (Bitfield-Mask: 0x01)                             */
#define I2C_STATUS0_READY_Pos             (3UL)                     /*!< READY (Bit 3)                                         */
#define I2C_STATUS0_READY_Msk             (0x8UL)                   /*!< READY (Bitfield-Mask: 0x01)                           */
#define I2C_STATUS0_ARBLOST_Pos           (4UL)                     /*!< ARBLOST (Bit 4)                                       */
#define I2C_STATUS0_ARBLOST_Msk           (0x10UL)                  /*!< ARBLOST (Bitfield-Mask: 0x01)                         */
#define I2C_STATUS0_BUSY_Pos              (5UL)                     /*!< BUSY (Bit 5)                                          */
#define I2C_STATUS0_BUSY_Msk              (0x20UL)                  /*!< BUSY (Bitfield-Mask: 0x01)                            */
#define I2C_STATUS0_SAMF_Pos              (6UL)                     /*!< SAMF (Bit 6)                                          */
#define I2C_STATUS0_SAMF_Msk              (0x40UL)                  /*!< SAMF (Bitfield-Mask: 0x01)                            */
#define I2C_STATUS0_BND_Pos               (7UL)                     /*!< BND (Bit 7)                                           */
#define I2C_STATUS0_BND_Msk               (0x80UL)                  /*!< BND (Bitfield-Mask: 0x01)                             */
/* ========================================================  STATUS1  ======================================================== */
#define I2C_STATUS1_TXEF_Pos              (0UL)                     /*!< TXEF (Bit 0)                                          */
#define I2C_STATUS1_TXEF_Msk              (0x1UL)                   /*!< TXEF (Bitfield-Mask: 0x01)                            */
#define I2C_STATUS1_RXFF_Pos              (1UL)                     /*!< RXFF (Bit 1)                                          */
#define I2C_STATUS1_RXFF_Msk              (0x2UL)                   /*!< RXFF (Bitfield-Mask: 0x01)                            */
#define I2C_STATUS1_TXUF_Pos              (2UL)                     /*!< TXUF (Bit 2)                                          */
#define I2C_STATUS1_TXUF_Msk              (0x4UL)                   /*!< TXUF (Bitfield-Mask: 0x01)                            */
#define I2C_STATUS1_RXOF_Pos              (3UL)                     /*!< RXOF (Bit 3)                                          */
#define I2C_STATUS1_RXOF_Msk              (0x8UL)                   /*!< RXOF (Bitfield-Mask: 0x01)                            */
/* ========================================================  DGLCFG  ========================================================= */
#define I2C_DGLCFG_DGL_CNT_Pos           (0UL)                     /*!< DGL_CNT (Bit 0)                                        */
#define I2C_DGLCFG_DGL_CNT_Msk           (0xfUL)                   /*!< DGL_CNT (Bitfield-Mask: 0x0f)                          */
#define I2C_DGLCFG_STARTF_Pos            (4UL)                     /*!< STARTF (Bit 4)                                         */
#define I2C_DGLCFG_STARTF_Msk            (0x10UL)                  /*!< STARTF (Bitfield-Mask: 0x01)                           */
#define I2C_DGLCFG_SSIE_Pos              (5UL)                     /*!< SSIE (Bit 5)                                           */
#define I2C_DGLCFG_SSIE_Msk              (0x20UL)                  /*!< SSIE (Bitfield-Mask: 0x01)                             */
#define I2C_DGLCFG_STOPF_Pos             (6UL)                     /*!< STOPF (Bit 6)                                          */
#define I2C_DGLCFG_STOPF_Msk             (0x40UL)                  /*!< STOPF (Bitfield-Mask: 0x01)                            */
#define I2C_DGLCFG_DGLEN_Pos             (7UL)                     /*!< DGLEN (Bit 7)                                          */
#define I2C_DGLCFG_DGLEN_Msk             (0x80UL)                  /*!< DGLEN (Bitfield-Mask: 0x01)                            */
/* =========================================================  DATA  ========================================================== */
#define I2C_DATA_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                           */
#define I2C_DATA_DATA_Msk                (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                             */
#define I2C_DATA_MAK_Pos                 (8UL)                     /*!< MAK (Bit 8)                                            */
#define I2C_DATA_MAK_Msk                 (0x100UL)                 /*!< MAK (Bitfield-Mask: 0x01)                              */
/* =======================================================  STARTSTOP  ======================================================= */
#define I2C_STARTSTOP_START_Pos          (0UL)                     /*!< START (Bit 0)                                          */
#define I2C_STARTSTOP_START_Msk          (0x1UL)                   /*!< START (Bitfield-Mask: 0x01)                            */
#define I2C_STARTSTOP_STOP_Pos           (1UL)                     /*!< STOP (Bit 1)                                           */
#define I2C_STARTSTOP_STOP_Msk           (0x2UL)                   /*!< STOP (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                           SPI                                             ================ */
/* =========================================================================================================================== */

/* =========================================================  CFG0  ========================================================== */
#define SPI_CFG0_SCK_HIGH_Pos             (0UL)                     /*!< SCK_HIGH (Bit 0)                                      */
#define SPI_CFG0_SCK_HIGH_Msk             (0xffUL)                  /*!< SCK_HIGH (Bitfield-Mask: 0xff)                        */
#define SPI_CFG0_SCK_LOW_Pos              (8UL)                     /*!< SCK_LOW (Bit 8)                                       */
#define SPI_CFG0_SCK_LOW_Msk              (0xff00UL)                /*!< SCK_LOW (Bitfield-Mask: 0xff)                         */
#define SPI_CFG0_CS_HOLD_Pos              (16UL)                    /*!< CS_HOLD (Bit 16)                                      */
#define SPI_CFG0_CS_HOLD_Msk              (0xff0000UL)              /*!< CS_HOLD (Bitfield-Mask: 0xff)                         */
#define SPI_CFG0_CS_SETUP_Pos             (24UL)                    /*!< CS_SETUP (Bit 24)                                     */
#define SPI_CFG0_CS_SETUP_Msk             (0xff000000UL)            /*!< CS_SETUP (Bitfield-Mask: 0xff)                        */
/* =========================================================  CFG1  ========================================================== */
#define SPI_CFG1_CS_IDLE_Pos              (0UL)                     /*!< CS_IDLE (Bit 0)                                       */
#define SPI_CFG1_CS_IDLE_Msk              (0xffUL)                  /*!< CS_IDLE (Bitfield-Mask: 0xff)                         */
#define SPI_CFG1_TXEIE_Pos                (8UL)                     /*!< TXEIE (Bit 8)                                         */
#define SPI_CFG1_TXEIE_Msk                (0x100UL)                 /*!< TXEIE (Bitfield-Mask: 0x01)                           */
#define SPI_CFG1_RXFIE_Pos                (9UL)                     /*!< RXFIE (Bit 9)                                         */
#define SPI_CFG1_RXFIE_Msk                (0x200UL)                 /*!< RXFIE (Bitfield-Mask: 0x01)                           */
#define SPI_CFG1_TXUIE_Pos                (10UL)                    /*!< TXUIE (Bit 10)                                        */
#define SPI_CFG1_TXUIE_Msk                (0x400UL)                 /*!< TXUIE (Bitfield-Mask: 0x01)                           */
#define SPI_CFG1_RXOIE_Pos                (11UL)                    /*!< RXOIE (Bit 11)                                        */
#define SPI_CFG1_RXOIE_Msk                (0x800UL)                 /*!< RXOIE (Bitfield-Mask: 0x01)                           */
#define SPI_CFG1_MSTR_Pos                 (12UL)                    /*!< MSTR (Bit 12)                                         */
#define SPI_CFG1_MSTR_Msk                 (0x1000UL)                /*!< MSTR (Bitfield-Mask: 0x01)                            */
#define SPI_CFG1_MODFIE_Pos               (13UL)                    /*!< MODFIE (Bit 13)                                       */
#define SPI_CFG1_MODFIE_Msk               (0x2000UL)                /*!< MODFIE (Bitfield-Mask: 0x01)                          */
#define SPI_CFG1_DMATXEN_Pos              (14UL)                    /*!< DMATXEN (Bit 14)                                      */
#define SPI_CFG1_DMATXEN_Msk              (0x4000UL)                /*!< DMATXEN (Bitfield-Mask: 0x01)                         */
#define SPI_CFG1_DMARXEN_Pos              (15UL)                    /*!< DMARXEN (Bit 15)                                      */
#define SPI_CFG1_DMARXEN_Msk              (0x8000UL)                /*!< DMARXEN (Bitfield-Mask: 0x01)                         */
#define SPI_CFG1_CPOL_Pos                 (16UL)                    /*!< CPOL (Bit 16)                                         */
#define SPI_CFG1_CPOL_Msk                 (0x10000UL)               /*!< CPOL (Bitfield-Mask: 0x01)                            */
#define SPI_CFG1_CPHA_Pos                 (17UL)                    /*!< CPHA (Bit 17)                                         */
#define SPI_CFG1_CPHA_Msk                 (0x20000UL)               /*!< CPHA (Bitfield-Mask: 0x01)                            */
#define SPI_CFG1_MSBF_Pos                 (18UL)                    /*!< MSBF (Bit 18)                                         */
#define SPI_CFG1_MSBF_Msk                 (0x40000UL)               /*!< MSBF (Bitfield-Mask: 0x01)                            */
#define SPI_CFG1_RMSBF_Pos                (19UL)                    /*!< RMSBF (Bit 19)                                        */
#define SPI_CFG1_RMSBF_Msk                (0x80000UL)               /*!< RMSBF (Bitfield-Mask: 0x01)                           */
#define SPI_CFG1_FRMSIZE_Pos              (20UL)                    /*!< FRMSIZE (Bit 20)                                      */
#define SPI_CFG1_FRMSIZE_Msk              (0xf00000UL)              /*!< FRMSIZE (Bitfield-Mask: 0x0f)                         */
#define SPI_CFG1_CSOE_Pos                 (25UL)                    /*!< CSOE (Bit 25)                                         */
#define SPI_CFG1_CSOE_Msk                 (0x2000000UL)             /*!< CSOE (Bitfield-Mask: 0x01)                            */
#define SPI_CFG1_MODFEN_Pos               (26UL)                    /*!< MODFEN (Bit 26)                                       */
#define SPI_CFG1_MODFEN_Msk               (0x4000000UL)             /*!< MODFEN (Bitfield-Mask: 0x01)                          */
#define SPI_CFG1_CONT_CS_Pos              (28UL)                    /*!< CONT_CS (Bit 28)                                      */
#define SPI_CFG1_CONT_CS_Msk              (0x10000000UL)            /*!< CONT_CS (Bitfield-Mask: 0x01)                         */
#define SPI_CFG1_WKUEN_Pos                (30UL)                    /*!< WKUEN (Bit 30)                                        */
#define SPI_CFG1_WKUEN_Msk                (0x40000000UL)            /*!< WKUEN (Bitfield-Mask: 0x01)                           */
/* ==========================================================  CMD  ========================================================== */
#define SPI_CMD_SPIEN_Pos                 (0UL)                     /*!< SPIEN (Bit 0)                                         */
#define SPI_CMD_SPIEN_Msk                 (0x1UL)                   /*!< SPIEN (Bitfield-Mask: 0x01)                           */
#define SPI_CMD_SWRST_Pos                 (4UL)                     /*!< SWRST (Bit 4)                                         */
#define SPI_CMD_SWRST_Msk                 (0x10UL)                  /*!< SWRST (Bitfield-Mask: 0x01)                           */
#define SPI_CMD_CSRLS_Pos                 (5UL)                     /*!< CSRLS (Bit 5)                                         */
#define SPI_CMD_CSRLS_Msk                 (0x20UL)                  /*!< CSRLS (Bitfield-Mask: 0x01)                           */
#define SPI_CMD_ROTRIG_Pos                (6UL)                     /*!< ROTRIG (Bit 6)                                        */
#define SPI_CMD_ROTRIG_Msk                (0x40UL)                  /*!< ROTRIG (Bitfield-Mask: 0x01)                          */
/* ========================================================  STATUS  ========================================================= */
#define SPI_STATUS_TXEF_Pos               (0UL)                     /*!< TXEF (Bit 0)                                          */
#define SPI_STATUS_TXEF_Msk               (0x1UL)                   /*!< TXEF (Bitfield-Mask: 0x01)                            */
#define SPI_STATUS_RXFF_Pos               (1UL)                     /*!< RXFF (Bit 1)                                          */
#define SPI_STATUS_RXFF_Msk               (0x2UL)                   /*!< RXFF (Bitfield-Mask: 0x01)                            */
#define SPI_STATUS_TXUF_Pos               (2UL)                     /*!< TXUF (Bit 2)                                          */
#define SPI_STATUS_TXUF_Msk               (0x4UL)                   /*!< TXUF (Bitfield-Mask: 0x01)                            */
#define SPI_STATUS_RXOF_Pos               (3UL)                     /*!< RXOF (Bit 3)                                          */
#define SPI_STATUS_RXOF_Msk               (0x8UL)                   /*!< RXOF (Bitfield-Mask: 0x01)                            */
#define SPI_STATUS_MODEF_Pos              (4UL)                     /*!< MODEF (Bit 4)                                         */
#define SPI_STATUS_MODEF_Msk              (0x10UL)                  /*!< MODEF (Bitfield-Mask: 0x01)                           */
#define SPI_STATUS_MEBY_Pos               (7UL)                     /*!< MEBY (Bit 7)                                          */
#define SPI_STATUS_MEBY_Msk               (0x80UL)                  /*!< MEBY (Bitfield-Mask: 0x01)                            */
#define SPI_STATUS_IDLEF_Pos              (8UL)                     /*!< IDLEF (Bit 8)                                         */
#define SPI_STATUS_IDLEF_Msk              (0x100UL)                 /*!< IDLEF (Bitfield-Mask: 0x01)                           */
/* =========================================================  DATA  ========================================================== */
#define SPI_DATA_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
#define SPI_DATA_DATA_Msk                 (0xffffUL)                /*!< DATA (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CFG2  ========================================================== */
#define SPI_CFG2_MNOV_Pos                 (1UL)                     /*!< MNOV (Bit 1)                                          */
#define SPI_CFG2_MNOV_Msk                 (0x2UL)                   /*!< MNOV (Bitfield-Mask: 0x01)                            */
#define SPI_CFG2_TOEN_Pos                 (2UL)                     /*!< TOEN (Bit 2)                                          */
#define SPI_CFG2_TOEN_Msk                 (0x4UL)                   /*!< TOEN (Bitfield-Mask: 0x01)                            */
#define SPI_CFG2_ROEN_Pos                 (3UL)                     /*!< ROEN (Bit 3)                                          */
#define SPI_CFG2_ROEN_Msk                 (0x8UL)                   /*!< ROEN (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ===============                                           ADC                                             ================= */
/* =========================================================================================================================== */

/* =========================================================  STR  =========================================================== */
#define ADC_STR_AMO_Pos                   (0UL)                     /*!< AMO (Bit 0)                                           */
#define ADC_STR_AMO_Msk                   (0x1UL)                   /*!< AMO (Bitfield-Mask: 0x01)                             */
#define ADC_STR_EOC_Pos                   (1UL)                     /*!< EOC (Bit 1)                                           */
#define ADC_STR_EOC_Msk                   (0x2UL)                   /*!< EOC (Bitfield-Mask: 0x01)                             */
#define ADC_STR_IEOC_Pos                  (2UL)                     /*!< IEOC (Bit 2)                                          */
#define ADC_STR_IEOC_Msk                  (0x4UL)                   /*!< IEOC (Bitfield-Mask: 0x01)                            */
#define ADC_STR_IDLE_Pos                  (4UL)                     /*!< IDLE (Bit 4)                                          */
#define ADC_STR_IDLE_Msk                  (0x10UL)                  /*!< IDLE (Bitfield-Mask: 0x01)                            */
#define ADC_STR_NAMO_Pos                  (5UL)                     /*!< NAMO (Bit 5)                                          */
#define ADC_STR_NAMO_Msk                  (0x20UL)                  /*!< NAMO (Bitfield-Mask: 0x01)                            */
#define ADC_STR_AAMO_Pos                  (6UL)                     /*!< AAMO (Bit 6)                                          */
#define ADC_STR_AAMO_Msk                  (0x40UL)                  /*!< AAMO (Bitfield-Mask: 0x01)                            */
/* =========================================================  CTRL0  ========================================================= */
#define ADC_CTRL0_AMOCH_Pos               (0UL)                     /*!< AMOCH (Bit 0)                                         */
#define ADC_CTRL0_AMOCH_Msk               (0x1fUL)                  /*!< AMOCH (Bitfield-Mask: 0x1f)                           */
#define ADC_CTRL0_AMOSGL_Pos              (5UL)                     /*!< AMOSGL (Bit 5)                                        */
#define ADC_CTRL0_AMOSGL_Msk              (0x20UL)                  /*!< AMOSGL (Bitfield-Mask: 0x01)                          */
#define ADC_CTRL0_IAMOEN_Pos              (6UL)                     /*!< IAMOEN (Bit 6)                                        */
#define ADC_CTRL0_IAMOEN_Msk              (0x40UL)                  /*!< IAMOEN (Bitfield-Mask: 0x01)                          */
#define ADC_CTRL0_AMOEN_Pos               (7UL)                     /*!< AMOEN (Bit 7)                                         */
#define ADC_CTRL0_AMOEN_Msk               (0x80UL)                  /*!< AMOEN (Bitfield-Mask: 0x01)                           */
#define ADC_CTRL0_DISCNUM_Pos             (8UL)                     /*!< DISCNUM (Bit 8)                                       */
#define ADC_CTRL0_DISCNUM_Msk             (0x700UL)                 /*!< DISCNUM (Bitfield-Mask: 0x07)                         */
#define ADC_CTRL0_IAUTO_Pos               (11UL)                    /*!< IAUTO (Bit 11)                                        */
#define ADC_CTRL0_IAUTO_Msk               (0x800UL)                 /*!< IAUTO (Bitfield-Mask: 0x01)                           */
#define ADC_CTRL0_IDISCEN_Pos             (12UL)                    /*!< IDISCEN (Bit 12)                                      */
#define ADC_CTRL0_IDISCEN_Msk             (0x1000UL)                /*!< IDISCEN (Bitfield-Mask: 0x01)                         */
#define ADC_CTRL0_DISCEN_Pos              (13UL)                    /*!< DISCEN (Bit 13)                                       */
#define ADC_CTRL0_DISCEN_Msk              (0x2000UL)                /*!< DISCEN (Bitfield-Mask: 0x01)                          */
#define ADC_CTRL0_CONT_Pos                (14UL)                    /*!< CONT (Bit 14)                                         */
#define ADC_CTRL0_CONT_Msk                (0x4000UL)                /*!< CONT (Bitfield-Mask: 0x01)                            */
#define ADC_CTRL0_SCAN_Pos                (15UL)                    /*!< SCAN (Bit 15)                                         */
#define ADC_CTRL0_SCAN_Msk                (0x8000UL)                /*!< SCAN (Bitfield-Mask: 0x01)                            */
#define ADC_CTRL0_EOCIE_Pos               (16UL)                    /*!< EOCIE (Bit 16)                                        */
#define ADC_CTRL0_EOCIE_Msk               (0x10000UL)               /*!< EOCIE (Bitfield-Mask: 0x01)                           */
#define ADC_CTRL0_IEOCIE_Pos              (17UL)                    /*!< IEOCIE (Bit 17)                                       */
#define ADC_CTRL0_IEOCIE_Msk              (0x20000UL)               /*!< IEOCIE (Bitfield-Mask: 0x01)                          */
#define ADC_CTRL0_AMOIE_Pos               (18UL)                    /*!< AMOIE (Bit 18)                                        */
#define ADC_CTRL0_AMOIE_Msk               (0x40000UL)               /*!< AMOIE (Bitfield-Mask: 0x01)                           */
#define ADC_CTRL0_DMAEN_Pos               (19UL)                    /*!< DMAEN (Bit 19)                                        */
#define ADC_CTRL0_DMAEN_Msk               (0x80000UL)               /*!< DMAEN (Bitfield-Mask: 0x01)                           */
#define ADC_CTRL0_EXTTRIG_Pos             (20UL)                    /*!< EXTTRIG (Bit 20)                                      */
#define ADC_CTRL0_EXTTRIG_Msk             (0x100000UL)              /*!< EXTTRIG (Bitfield-Mask: 0x01)                         */
#define ADC_CTRL0_IEXTTRIG_Pos            (21UL)                    /*!< IEXTTRIG (Bit 21)                                     */
#define ADC_CTRL0_IEXTTRIG_Msk            (0x200000UL)              /*!< IEXTTRIG (Bitfield-Mask: 0x01)                        */
#define ADC_CTRL0_ALIGN_Pos               (22UL)                    /*!< ALIGN (Bit 22)                                        */
#define ADC_CTRL0_ALIGN_Msk               (0x400000UL)              /*!< ALIGN (Bitfield-Mask: 0x01)                           */
#define ADC_CTRL0_AMOMODE_Pos             (23UL)                    /*!< AMOMODE (Bit 23)                                      */
#define ADC_CTRL0_AMOMODE_Msk             (0x800000UL)              /*!< AMOMODE (Bitfield-Mask: 0x01)                         */
#define ADC_CTRL0_INTERVAL_Pos            (24UL)                    /*!< INTERVAL (Bit 24)                                     */
#define ADC_CTRL0_INTERVAL_Msk            (0x1000000UL)             /*!< INTERVAL (Bitfield-Mask: 0x01)                        */
#define ADC_CTRL0_ISWSTART_Pos            (30UL)                    /*!< ISWSTART (Bit 30)                                     */
#define ADC_CTRL0_ISWSTART_Msk            (0x40000000UL)            /*!< ISWSTART (Bitfield-Mask: 0x01)                        */
#define ADC_CTRL0_SWSTART_Pos             (31UL)                    /*!< SWSTART (Bit 31)                                      */
#define ADC_CTRL0_SWSTART_Msk             (0x80000000UL)            /*!< SWSTART (Bitfield-Mask: 0x01)                         */
/* =========================================================  CTRL1  ========================================================= */
#define ADC_CTRL1_ADON_Pos                (0UL)                     /*!< ADON (Bit 0)                                          */
#define ADC_CTRL1_ADON_Msk                (0x1UL)                   /*!< ADON (Bitfield-Mask: 0x01)                            */
#define ADC_CTRL1_CALEN_Pos               (1UL)                     /*!< CALEN (Bit 1)                                         */
#define ADC_CTRL1_CALEN_Msk               (0x2UL)                   /*!< CALEN (Bitfield-Mask: 0x01)                           */
#define ADC_CTRL1_PSC_Pos                 (12UL)                    /*!< PSC (Bit 12)                                          */
#define ADC_CTRL1_PSC_Msk                 (0xf000UL)                /*!< PSC (Bitfield-Mask: 0x0f)                             */
/* =========================================================  SPT0  ========================================================== */
#define ADC_SPT0_SPT10_Pos                (0UL)                     /*!< SPT10 (Bit 0)                                         */
#define ADC_SPT0_SPT10_Msk                (0x7UL)                   /*!< SPT10 (Bitfield-Mask: 0x07)                           */
#define ADC_SPT0_SPT11_Pos                (3UL)                     /*!< SPT11 (Bit 3)                                         */
#define ADC_SPT0_SPT11_Msk                (0x38UL)                  /*!< SPT11 (Bitfield-Mask: 0x07)                           */
#define ADC_SPT0_SPT12_Pos                (6UL)                     /*!< SPT12 (Bit 6)                                         */
#define ADC_SPT0_SPT12_Msk                (0x1c0UL)                 /*!< SPT12 (Bitfield-Mask: 0x07)                           */
#define ADC_SPT0_SPT13_Pos                (9UL)                     /*!< SPT13 (Bit 9)                                         */
#define ADC_SPT0_SPT13_Msk                (0xe00UL)                 /*!< SPT13 (Bitfield-Mask: 0x07)                           */
/* =========================================================  SPT1  ========================================================== */
#define ADC_SPT1_SPT0_Pos                 (0UL)                     /*!< SPT0 (Bit 0)                                          */
#define ADC_SPT1_SPT0_Msk                 (0x7UL)                   /*!< SPT0 (Bitfield-Mask: 0x07)                            */
#define ADC_SPT1_SPT1_Pos                 (3UL)                     /*!< SPT1 (Bit 3)                                          */
#define ADC_SPT1_SPT1_Msk                 (0x38UL)                  /*!< SPT1 (Bitfield-Mask: 0x07)                            */
#define ADC_SPT1_SPT2_Pos                 (6UL)                     /*!< SPT2 (Bit 6)                                          */
#define ADC_SPT1_SPT2_Msk                 (0x1c0UL)                 /*!< SPT2 (Bitfield-Mask: 0x07)                            */
#define ADC_SPT1_SPT3_Pos                 (9UL)                     /*!< SPT3 (Bit 9)                                          */
#define ADC_SPT1_SPT3_Msk                 (0xe00UL)                 /*!< SPT3 (Bitfield-Mask: 0x07)                            */
#define ADC_SPT1_SPT4_Pos                 (12UL)                    /*!< SPT4 (Bit 12)                                         */
#define ADC_SPT1_SPT4_Msk                 (0x7000UL)                /*!< SPT4 (Bitfield-Mask: 0x07)                            */
#define ADC_SPT1_SPT5_Pos                 (15UL)                    /*!< SPT5 (Bit 15)                                         */
#define ADC_SPT1_SPT5_Msk                 (0x38000UL)               /*!< SPT5 (Bitfield-Mask: 0x07)                            */
#define ADC_SPT1_SPT6_Pos                 (18UL)                    /*!< SPT6 (Bit 18)                                         */
#define ADC_SPT1_SPT6_Msk                 (0x1c0000UL)              /*!< SPT6 (Bitfield-Mask: 0x07)                            */
#define ADC_SPT1_SPT7_Pos                 (21UL)                    /*!< SPT7 (Bit 21)                                         */
#define ADC_SPT1_SPT7_Msk                 (0xe00000UL)              /*!< SPT7 (Bitfield-Mask: 0x07)                            */
#define ADC_SPT1_SPT8_Pos                 (24UL)                    /*!< SPT8 (Bit 24)                                         */
#define ADC_SPT1_SPT8_Msk                 (0x7000000UL)             /*!< SPT8 (Bitfield-Mask: 0x07)                            */
#define ADC_SPT1_SPT9_Pos                 (27UL)                    /*!< SPT9 (Bit 27)                                         */
#define ADC_SPT1_SPT9_Msk                 (0x38000000UL)            /*!< SPT9 (Bitfield-Mask: 0x07)                            */
#define ADC_SPT_Msk                       (0x7UL)                   /*!< SPT  (Bitfield-Mask: 0x07)                            */
#define ADC_SPT_Width                     (3UL)                     /*!< SPT width (3bit)                                      */
/* =========================================================  IOFR  ========================================================== */
#define ADC_IOFR_IOFR_Pos                 (0UL)                     /*!< IOFR (Bit 0)                                          */
#define ADC_IOFR_IOFR_Msk                 (0xfffUL)                 /*!< IOFR (Bitfield-Mask: 0xfff)                           */
/* =========================================================  AMOHR  ========================================================= */
#define ADC_AMOHR_AMOHT_Pos               (0UL)                     /*!< AMOHT (Bit 0)                                         */
#define ADC_AMOHR_AMOHT_Msk               (0xfffUL)                 /*!< AMOHT (Bitfield-Mask: 0xfff)                          */
#define ADC_AMOHR_AMOHO_Pos               (16UL)                    /*!< AMOHO (Bit 16)                                        */
#define ADC_AMOHR_AMOHO_Msk               (0xfff0000UL)             /*!< AMOHO (Bitfield-Mask: 0xfff)                          */
/* =========================================================  AMOLR  ========================================================= */
#define ADC_AMOLR_AMOLT_Pos               (0UL)                     /*!< AMOLT (Bit 0)                                         */
#define ADC_AMOLR_AMOLT_Msk               (0xfffUL)                 /*!< AMOLT (Bitfield-Mask: 0xfff)                          */
#define ADC_AMOLR_AMOLO_Pos               (16UL)                    /*!< AMOLO (Bit 16)                                        */
#define ADC_AMOLR_AMOLO_Msk               (0xfff0000UL)             /*!< AMOLO (Bitfield-Mask: 0xfff)                          */
/* =========================================================  RSQR0  ========================================================= */
#define ADC_RSQR0_RSQ12_Pos               (0UL)                     /*!< RSQ12 (Bit 0)                                         */
#define ADC_RSQR0_RSQ12_Msk               (0x1fUL)                  /*!< RSQ12 (Bitfield-Mask: 0x1f)                           */
#define ADC_RSQR0_RSQ13_Pos               (5UL)                     /*!< RSQ13 (Bit 5)                                         */
#define ADC_RSQR0_RSQ13_Msk               (0x3e0UL)                 /*!< RSQ13 (Bitfield-Mask: 0x1f)                           */
#define ADC_RSQR0_RSQL_Pos                (20UL)                    /*!< RSQL (Bit 20)                                         */
#define ADC_RSQR0_RSQL_Msk                (0xf00000UL)              /*!< RSQL (Bitfield-Mask: 0x0f)                            */
/* =========================================================  RSQR1  ========================================================= */
#define ADC_RSQR1_RSQ6_Pos                (0UL)                     /*!< RSQ6 (Bit 0)                                          */
#define ADC_RSQR1_RSQ6_Msk                (0x1fUL)                  /*!< RSQ6 (Bitfield-Mask: 0x1f)                            */
#define ADC_RSQR1_RSQ7_Pos                (5UL)                     /*!< RSQ7 (Bit 5)                                          */
#define ADC_RSQR1_RSQ7_Msk                (0x3e0UL)                 /*!< RSQ7 (Bitfield-Mask: 0x1f)                            */
#define ADC_RSQR1_RSQ8_Pos                (10UL)                    /*!< RSQ8 (Bit 10)                                         */
#define ADC_RSQR1_RSQ8_Msk                (0x7c00UL)                /*!< RSQ8 (Bitfield-Mask: 0x1f)                            */
#define ADC_RSQR1_RSQ9_Pos                (15UL)                    /*!< RSQ9 (Bit 15)                                         */
#define ADC_RSQR1_RSQ9_Msk                (0xf8000UL)               /*!< RSQ9 (Bitfield-Mask: 0x1f)                            */
#define ADC_RSQR1_RSQ10_Pos               (20UL)                    /*!< RSQ10 (Bit 20)                                        */
#define ADC_RSQR1_RSQ10_Msk               (0x1f00000UL)             /*!< RSQ10 (Bitfield-Mask: 0x1f)                           */
#define ADC_RSQR1_RSQ11_Pos               (25UL)                    /*!< RSQ11 (Bit 25)                                        */
#define ADC_RSQR1_RSQ11_Msk               (0x3e000000UL)            /*!< RSQ11 (Bitfield-Mask: 0x1f)                           */
/* =========================================================  RSQR2  ========================================================= */
#define ADC_RSQR2_RSQ0_Pos                (0UL)                     /*!< RSQ0 (Bit 0)                                          */
#define ADC_RSQR2_RSQ0_Msk                (0x1fUL)                  /*!< RSQ0 (Bitfield-Mask: 0x1f)                            */
#define ADC_RSQR2_RSQ1_Pos                (5UL)                     /*!< RSQ1 (Bit 5)                                          */
#define ADC_RSQR2_RSQ1_Msk                (0x3e0UL)                 /*!< RSQ1 (Bitfield-Mask: 0x1f)                            */
#define ADC_RSQR2_RSQ2_Pos                (10UL)                    /*!< RSQ2 (Bit 10)                                         */
#define ADC_RSQR2_RSQ2_Msk                (0x7c00UL)                /*!< RSQ2 (Bitfield-Mask: 0x1f)                            */
#define ADC_RSQR2_RSQ3_Pos                (15UL)                    /*!< RSQ3 (Bit 15)                                         */
#define ADC_RSQR2_RSQ3_Msk                (0xf8000UL)               /*!< RSQ3 (Bitfield-Mask: 0x1f)                            */
#define ADC_RSQR2_RSQ4_Pos                (20UL)                    /*!< RSQ4 (Bit 20)                                         */
#define ADC_RSQR2_RSQ4_Msk                (0x1f00000UL)             /*!< RSQ4 (Bitfield-Mask: 0x1f)                            */
#define ADC_RSQR2_RSQ5_Pos                (25UL)                    /*!< RSQ5 (Bit 25)                                         */
#define ADC_RSQR2_RSQ5_Msk                (0x3e000000UL)            /*!< RSQ5 (Bitfield-Mask: 0x1f)                            */
#define ADC_SQ_Msk                        (0x1fUL)                  /*!< SQ  (Bitfield-Mask: 0x1f)                             */
#define ADC_SQ_Width                      (5UL)                     /*!< SQ width (5bit)                                       */
/* =========================================================  ISQR  ========================================================== */
#define ADC_ISQR_ISQ0_Pos                 (0UL)                     /*!< ISQ0 (Bit 0)                                          */
#define ADC_ISQR_ISQ0_Msk                 (0x1fUL)                  /*!< ISQ0 (Bitfield-Mask: 0x1f)                            */
#define ADC_ISQR_ISQ1_Pos                 (5UL)                     /*!< ISQ1 (Bit 5)                                          */
#define ADC_ISQR_ISQ1_Msk                 (0x3e0UL)                 /*!< ISQ1 (Bitfield-Mask: 0x1f)                            */
#define ADC_ISQR_ISQ2_Pos                 (10UL)                    /*!< ISQ2 (Bit 10)                                         */
#define ADC_ISQR_ISQ2_Msk                 (0x7c00UL)                /*!< ISQ2 (Bitfield-Mask: 0x1f)                            */
#define ADC_ISQR_ISQ3_Pos                 (15UL)                    /*!< ISQ3 (Bit 15)                                         */
#define ADC_ISQR_ISQ3_Msk                 (0xf8000UL)               /*!< ISQ3 (Bitfield-Mask: 0x1f)                            */
#define ADC_ISQR_ISQL_Pos                 (20UL)                    /*!< ISQL (Bit 20)                                         */
#define ADC_ISQR_ISQL_Msk                 (0x300000UL)              /*!< ISQL (Bitfield-Mask: 0x03)                            */
/* =========================================================  IDR   ========================================================== */
#define ADC_IDR_IDR_Pos                   (0UL)                     /*!< IDR (Bit 0)                                           */
#define ADC_IDR_IDR_Msk                   (0xfffUL)                 /*!< IDR (Bitfield-Mask: 0xfff)                            */
/* ==========================================================  RDR  ========================================================== */
#define ADC_RDR_RDR_Pos                   (0UL)                     /*!< RDR (Bit 0)                                           */
#define ADC_RDR_RDR_Msk                   (0xfffUL)                 /*!< RDR (Bitfield-Mask: 0xfff)                            */


/* =========================================================================================================================== */
/* ================                                        ACMP_ANACFG                                        ================ */
/* =========================================================================================================================== */

/* =========================================================  CFG0  ========================================================== */
#define ACMP_ANACFG_CFG0_LPF_Pos          (21UL)                    /*!< LPF (Bit 21)                                          */
#define ACMP_ANACFG_CFG0_LPF_Msk          (0x600000UL)              /*!< LPF (Bitfield-Mask: 0x02)                             */
#define ACMP_ANACFG_CFG0_HYST_Pos         (23UL)                    /*!< HYST (Bit 23)                                         */
#define ACMP_ANACFG_CFG0_HYST_Msk         (0x800000UL)              /*!< HYST (Bitfield-Mask: 0x01)                            */                         


/* =========================================================================================================================== */
/* ================                                           ACMP                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR0  ========================================================== */
#define ACMP_CR0_MOD_Pos                  (0UL)                     /*!< MOD (Bit 0)                                           */
#define ACMP_CR0_MOD_Msk                  (0x3UL)                   /*!< MOD (Bitfield-Mask: 0x03)                             */
#define ACMP_CR0_OPE_Pos                  (2UL)                     /*!< OPE (Bit 2)                                           */
#define ACMP_CR0_OPE_Msk                  (0x4UL)                   /*!< OPE (Bitfield-Mask: 0x01)                             */
#define ACMP_CR0_OUTEN_Pos                (3UL)                     /*!< OUTEN (Bit 3)                                         */
#define ACMP_CR0_OUTEN_Msk                (0x8UL)                   /*!< OUTEN (Bitfield-Mask: 0x01)                           */
#define ACMP_CR0_IE_Pos                   (4UL)                     /*!< IE (Bit 4)                                            */
#define ACMP_CR0_IE_Msk                   (0x10UL)                  /*!< IE (Bitfield-Mask: 0x01)                              */
#define ACMP_CR0_EN_Pos                   (7UL)                     /*!< EN (Bit 7)                                            */
#define ACMP_CR0_EN_Msk                   (0x80UL)                  /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CR1  ========================================================== */
#define ACMP_CR1_NSEL_Pos                 (0UL)                     /*!< NSEL (Bit 0)                                          */
#define ACMP_CR1_NSEL_Msk                 (0xfUL)                   /*!< NSEL (Bitfield-Mask: 0x0f)                            */
#define ACMP_CR1_PSEL_Pos                 (4UL)                     /*!< PSEL (Bit 4)                                          */
#define ACMP_CR1_PSEL_Msk                 (0xf0UL)                  /*!< PSEL (Bitfield-Mask: 0x0f)                            */
/* ==========================================================  CR2  ========================================================== */
#define ACMP_CR2_DACVAL_Pos               (0UL)                     /*!< DACVAL (Bit 0)                                        */
#define ACMP_CR2_DACVAL_Msk               (0x3fUL)                  /*!< DACVAL (Bitfield-Mask: 0x3f)                          */
#define ACMP_CR2_DACEN_Pos                (7UL)                     /*!< DACEN (Bit 7)                                         */
#define ACMP_CR2_DACEN_Msk                (0x80UL)                  /*!< DACEN (Bitfield-Mask: 0x01)                           */
/* ==========================================================  CR3  ========================================================== */
#define ACMP_CR3_NSPLEN_Pos               (3UL)                     /*!< NSPLEN (Bit 3)                                        */
#define ACMP_CR3_NSPLEN_Msk               (0x8UL)                   /*!< NSPLEN (Bitfield-Mask: 0x01)                          */
#define ACMP_CR3_PSPLEN_Pos               (7UL)                     /*!< PSPLEN (Bit 7)                                        */
#define ACMP_CR3_PSPLEN_Msk               (0x80UL)                  /*!< PSPLEN (Bitfield-Mask: 0x01)                          */
/* ==========================================================  CR4  ========================================================== */
#define ACMP_CR4_PLSEQ_Pos                (0UL)                     /*!< PLSEQ (Bit 0)                                         */
#define ACMP_CR4_PLSEQ_Msk                (0xffUL)                  /*!< PLSEQ (Bitfield-Mask: 0xff)                           */
/* ==========================================================  DR  =========================================================== */
#define ACMP_DR_O0_Pos                    (0UL)                     /*!< O0 (Bit 0)                                            */
#define ACMP_DR_O0_Msk                    (0x1UL)                   /*!< O0 (Bitfield-Mask: 0x01)                              */
#define ACMP_DR_O1_Pos                    (1UL)                     /*!< O1 (Bit 1)                                            */
#define ACMP_DR_O1_Msk                    (0x2UL)                   /*!< O1 (Bitfield-Mask: 0x01)                              */
#define ACMP_DR_O2_Pos                    (2UL)                     /*!< O2 (Bit 2)                                            */
#define ACMP_DR_O2_Msk                    (0x4UL)                   /*!< O2 (Bitfield-Mask: 0x01)                              */
#define ACMP_DR_O3_Pos                    (3UL)                     /*!< O3 (Bit 3)                                            */
#define ACMP_DR_O3_Msk                    (0x8UL)                   /*!< O3 (Bitfield-Mask: 0x01)                              */
#define ACMP_DR_O4_Pos                    (4UL)                     /*!< O4 (Bit 4)                                            */
#define ACMP_DR_O4_Msk                    (0x10UL)                  /*!< O4 (Bitfield-Mask: 0x01)                              */
#define ACMP_DR_O5_Pos                    (5UL)                     /*!< O5 (Bit 5)                                            */
#define ACMP_DR_O5_Msk                    (0x20UL)                  /*!< O5 (Bitfield-Mask: 0x01)                              */
#define ACMP_DR_O6_Pos                    (6UL)                     /*!< O6 (Bit 6)                                            */
#define ACMP_DR_O6_Msk                    (0x40UL)                  /*!< O6 (Bitfield-Mask: 0x01)                              */
#define ACMP_DR_O7_Pos                    (7UL)                     /*!< O7 (Bit 7)                                            */
#define ACMP_DR_O7_Msk                    (0x80UL)                  /*!< O7 (Bitfield-Mask: 0x01)                              */
#define ACMP_DR_O_Pos                     (8UL)                     /*!< O (Bit 8)                                             */
#define ACMP_DR_O_Msk                     (0x100UL)                 /*!< O (Bitfield-Mask: 0x01)                               */
#define ACMP_DR_POLLING_O_Msk             (0xffUL)                  /*!< POLLING O (Bitfield-Mask: 0xff)                       */
/* ==========================================================  SR  =========================================================== */
#define ACMP_SR_F0_Pos                    (0UL)                     /*!< F0 (Bit 0)                                            */
#define ACMP_SR_F0_Msk                    (0x1UL)                   /*!< F0 (Bitfield-Mask: 0x01)                              */
#define ACMP_SR_F1_Pos                    (1UL)                     /*!< F1 (Bit 1)                                            */
#define ACMP_SR_F1_Msk                    (0x2UL)                   /*!< F1 (Bitfield-Mask: 0x01)                              */
#define ACMP_SR_F2_Pos                    (2UL)                     /*!< F2 (Bit 2)                                            */
#define ACMP_SR_F2_Msk                    (0x4UL)                   /*!< F2 (Bitfield-Mask: 0x01)                              */
#define ACMP_SR_F3_Pos                    (3UL)                     /*!< F3 (Bit 3)                                            */
#define ACMP_SR_F3_Msk                    (0x8UL)                   /*!< F3 (Bitfield-Mask: 0x01)                              */
#define ACMP_SR_F4_Pos                    (4UL)                     /*!< F4 (Bit 4)                                            */
#define ACMP_SR_F4_Msk                    (0x10UL)                  /*!< F4 (Bitfield-Mask: 0x01)                              */
#define ACMP_SR_F5_Pos                    (5UL)                     /*!< F5 (Bit 5)                                            */
#define ACMP_SR_F5_Msk                    (0x20UL)                  /*!< F5 (Bitfield-Mask: 0x01)                              */
#define ACMP_SR_F6_Pos                    (6UL)                     /*!< F6 (Bit 6)                                            */
#define ACMP_SR_F6_Msk                    (0x40UL)                  /*!< F6 (Bitfield-Mask: 0x01)                              */
#define ACMP_SR_F7_Pos                    (7UL)                     /*!< F7 (Bit 7)                                            */
#define ACMP_SR_F7_Msk                    (0x80UL)                  /*!< F7 (Bitfield-Mask: 0x01)                              */
#define ACMP_SR_F_Pos                     (8UL)                     /*!< F (Bit 8)                                             */
#define ACMP_SR_F_Msk                     (0x100UL)                 /*!< F (Bitfield-Mask: 0x01)                               */
#define ACMP_SR_WPF_Pos                   (9UL)                     /*!< WPF (Bit 9)                                           */
#define ACMP_SR_WPF_Msk                   (0x200UL)                 /*!< WPF (Bitfield-Mask: 0x01)                             */
#define ACMP_SR_POLLING_F_Msk             (0xFFUL)                  /*!< POLLING STATUS (Bitfield-Mask: 0xff)                  */
/* ==========================================================  FD  =========================================================== */
#define ACMP_FD_PLFD_Pos                  (0UL)                     /*!< PLFD (Bit 0)                                          */
#define ACMP_FD_PLFD_Msk                  (0x3UL)                   /*!< PLFD (Bitfield-Mask: 0x03)                            */
/* ==========================================================  OPA  ========================================================== */
#define ACMP_OPA_OPASEL_Pos               (0UL)                     /*!< OPASEL (Bit 0)                                        */
#define ACMP_OPA_OPASEL_Msk               (0x7UL)                   /*!< OPASEL (Bitfield-Mask: 0x07)                          */
/* ==========================================================  OPB  ========================================================== */
#define ACMP_OPB_OPBSEL_Pos               (0UL)                     /*!< OPBSEL (Bit 0)                                        */
#define ACMP_OPB_OPBSEL_Msk               (0x7UL)                   /*!< OPBSEL (Bitfield-Mask: 0x07)                          */
/* ==========================================================  OPC  ========================================================== */
#define ACMP_OPC_OPCSEL_Pos               (0UL)                     /*!< OPCSEL (Bit 0)                                        */
#define ACMP_OPC_OPCSEL_Msk               (0x7UL)                   /*!< OPCSEL (Bitfield-Mask: 0x07)                          */
/* =========================================================  DACSR  ========================================================= */
#define ACMP_DACSR_DACREF_Pos             (0UL)                     /*!< DACREF (Bit 0)                                        */
#define ACMP_DACSR_DACREF_Msk             (0x1UL)                   /*!< DACREF (Bitfield-Mask: 0x01)                          */


/* =========================================================================================================================== */
/* ===============                                           PWM                                             ================= */
/* =========================================================================================================================== */

/* =========================================================  INIT  ========================================================== */
#define PWM_INIT_CLKSRC_Pos               (3UL)                     /*!< CLKSRC (Bit 3)                                        */
#define PWM_INIT_CLKSRC_Msk               (0x18UL)                  /*!< CLKSRC (Bitfield-Mask: 0x03)                          */
#define PWM_INIT_CNTMODE_Pos              (5UL)                     /*!< CNTMODE (Bit 5)                                       */
#define PWM_INIT_CNTMODE_Msk              (0x20UL)                  /*!< CNTMODE (Bitfield-Mask: 0x01)                         */
#define PWM_INIT_CNTOIE_Pos               (6UL)                     /*!< CNTOIE (Bit 6)                                        */
#define PWM_INIT_CNTOIE_Msk               (0x40UL)                  /*!< CNTOIE (Bitfield-Mask: 0x01)                          */
#define PWM_INIT_CNTOF_Pos                (7UL)                     /*!< CNTOF (Bit 7)                                         */
#define PWM_INIT_CNTOF_Msk                (0x80UL)                  /*!< CNTOF (Bitfield-Mask: 0x01)                           */
#define PWM_INIT_CLKPSC_Pos               (8UL)                     /*!< CLKPSC (Bit 8)                                        */
#define PWM_INIT_CLKPSC_Msk               (0xffff00UL)              /*!< CLKPSC (Bitfield-Mask: 0xffff)                        */
/* ==========================================================  CNT  ========================================================== */
#define PWM_CNT_COUNT_Pos                 (0UL)                     /*!< COUNT (Bit 0)                                         */
#define PWM_CNT_COUNT_Msk                 (0xffffUL)                /*!< COUNT (Bitfield-Mask: 0xffff)                         */
/* =========================================================  MCVR  ========================================================== */
#define PWM_MCVR_MCVR_Pos                 (0UL)                     /*!< MCVR (Bit 0)                                          */
#define PWM_MCVR_MCVR_Msk                 (0xffffUL)                /*!< MCVR (Bitfield-Mask: 0xffff)                          */
/* ========================================================  CH0SCR  ========================================================= */
#define PWM_CHSCR_DIR_Pos                 (1UL)                     /*!< DIR (Bit 1)                                           */
#define PWM_CHSCR_DIR_Msk                 (0x2UL)                   /*!< DIR (Bitfield-Mask: 0x01)                             */
#define PWM_CHSCR_ELSR0_Pos               (2UL)                     /*!< ELSR0 (Bit 2)                                         */
#define PWM_CHSCR_ELSR0_Msk               (0x4UL)                   /*!< ELSR0 (Bitfield-Mask: 0x01)                           */
#define PWM_CHSCR_ELSR1_Pos               (3UL)                     /*!< ELSR1 (Bit 3)                                         */
#define PWM_CHSCR_ELSR1_Msk               (0x8UL)                   /*!< ELSR1 (Bitfield-Mask: 0x01)                           */
#define PWM_CHSCR_MSR0_Pos                (4UL)                     /*!< MSR0 (Bit 4)                                          */
#define PWM_CHSCR_MSR0_Msk                (0x10UL)                  /*!< MSR0 (Bitfield-Mask: 0x01)                            */
#define PWM_CHSCR_MSR1_Pos                (5UL)                     /*!< MSR1 (Bit 5)                                          */
#define PWM_CHSCR_MSR1_Msk                (0x20UL)                  /*!< MSR1 (Bitfield-Mask: 0x01)                            */
#define PWM_CHSCR_CHIE_Pos                (6UL)                     /*!< CHIE (Bit 6)                                          */
#define PWM_CHSCR_CHIE_Msk                (0x40UL)                  /*!< CHIE (Bitfield-Mask: 0x01)                            */
#define PWM_CHSCR_CHIF_Pos                (7UL)                     /*!< CHIF (Bit 7)                                          */
#define PWM_CHSCR_CHIF_Msk                (0x80UL)                  /*!< CHIF (Bitfield-Mask: 0x01)                            */
/* =========================================================  CH0V  ========================================================== */
#define PWM_CHV_CHCVAL_Pos                (0UL)                     /*!< CHCVAL (Bit 0)                                        */
#define PWM_CHV_CHCVAL_Msk                (0xffffUL)                /*!< CHCVAL (Bitfield-Mask: 0xffff)                        */
/* =========================================================  CNTIN  ========================================================= */
#define PWM_CNTIN_CNTINIT_Pos             (0UL)                     /*!< CNTINIT (Bit 0)                                       */
#define PWM_CNTIN_CNTINIT_Msk             (0xffffUL)                /*!< CNTINIT (Bitfield-Mask: 0xffff)                       */
/* ==========================================================  STR  ========================================================== */
#define PWM_STR_CH0SF_Pos                 (0UL)                     /*!< CH0SF (Bit 0)                                         */
#define PWM_STR_CH0SF_Msk                 (0x1UL)                   /*!< CH0SF (Bitfield-Mask: 0x01)                           */
#define PWM_STR_CH1SF_Pos                 (1UL)                     /*!< CH1SF (Bit 1)                                         */
#define PWM_STR_CH1SF_Msk                 (0x2UL)                   /*!< CH1SF (Bitfield-Mask: 0x01)                           */
#define PWM_STR_CH2SF_Pos                 (2UL)                     /*!< CH2SF (Bit 2)                                         */
#define PWM_STR_CH2SF_Msk                 (0x4UL)                   /*!< CH2SF (Bitfield-Mask: 0x01)                           */
#define PWM_STR_CH3SF_Pos                 (3UL)                     /*!< CH3SF (Bit 3)                                         */
#define PWM_STR_CH3SF_Msk                 (0x8UL)                   /*!< CH3SF (Bitfield-Mask: 0x01)                           */
#define PWM_STR_CH4SF_Pos                 (4UL)                     /*!< CH4SF (Bit 4)                                         */
#define PWM_STR_CH4SF_Msk                 (0x10UL)                  /*!< CH4SF (Bitfield-Mask: 0x01)                           */
#define PWM_STR_CH5SF_Pos                 (5UL)                     /*!< CH5SF (Bit 5)                                         */
#define PWM_STR_CH5SF_Msk                 (0x20UL)                  /*!< CH5SF (Bitfield-Mask: 0x01)                           */
#define PWM_STR_CH6SF_Pos                 (6UL)                     /*!< CH6SF (Bit 6)                                         */
#define PWM_STR_CH6SF_Msk                 (0x40UL)                  /*!< CH6SF (Bitfield-Mask: 0x01)                           */
#define PWM_STR_CH7SF_Pos                 (7UL)                     /*!< CH7SF (Bit 7)                                         */
#define PWM_STR_CH7SF_Msk                 (0x80UL)                  /*!< CH7SF (Bitfield-Mask: 0x01)                           */
#define PWM_STR_CHSF_Msk                  (0xffUL)                  /*!< CHSF  (Bitfield-Mask: 0xff)                           */
/* ========================================================  FUNCSEL  ======================================================== */
#define PWM_FUNCSEL_PWMSYNCEN_Pos         (0UL)                     /*!< PWMSYNCEN (Bit 0)                                     */
#define PWM_FUNCSEL_PWMSYNCEN_Msk         (0x1UL)                   /*!< PWMSYNCEN (Bitfield-Mask: 0x01)                       */
#define PWM_FUNCSEL_INIT_Pos              (1UL)                     /*!< INIT (Bit 1)                                          */
#define PWM_FUNCSEL_INIT_Msk              (0x2UL)                   /*!< INIT (Bitfield-Mask: 0x01)                            */
#define PWM_FUNCSEL_WPDIS_Pos             (2UL)                     /*!< WPDIS (Bit 2)                                         */
#define PWM_FUNCSEL_WPDIS_Msk             (0x4UL)                   /*!< WPDIS (Bitfield-Mask: 0x01)                           */
#define PWM_FUNCSEL_PWMSYNC_Pos           (3UL)                     /*!< PWMSYNC (Bit 3)                                       */
#define PWM_FUNCSEL_PWMSYNC_Msk           (0x8UL)                   /*!< PWMSYNC (Bitfield-Mask: 0x01)                         */
#define PWM_FUNCSEL_FAULTMODE_Pos         (5UL)                     /*!< FAULTMODE (Bit 5)                                     */
#define PWM_FUNCSEL_FAULTMODE_Msk         (0x60UL)                  /*!< FAULTMODE (Bitfield-Mask: 0x03)                       */
#define PWM_FUNCSEL_FAULTIE_Pos           (7UL)                     /*!< FAULTIE (Bit 7)                                       */
#define PWM_FUNCSEL_FAULTIE_Msk           (0x80UL)                  /*!< FAULTIE (Bitfield-Mask: 0x01)                         */
/* =========================================================  SYNC  ========================================================== */
#define PWM_SYNC_MINSYNCP_Pos             (0UL)                     /*!< MINSYNCP (Bit 0)                                      */
#define PWM_SYNC_MINSYNCP_Msk             (0x1UL)                   /*!< MINSYNCP (Bitfield-Mask: 0x01)                        */
#define PWM_SYNC_MAXSYNCP_Pos             (1UL)                     /*!< MAXSYNCP (Bit 1)                                      */
#define PWM_SYNC_MAXSYNCP_Msk             (0x2UL)                   /*!< MAXSYNCP (Bitfield-Mask: 0x01)                        */
#define PWM_SYNC_OMSYNCP_Pos              (3UL)                     /*!< OMSYNCP (Bit 3)                                       */
#define PWM_SYNC_OMSYNCP_Msk              (0x8UL)                   /*!< OMSYNCP (Bitfield-Mask: 0x01)                         */
#define PWM_SYNC_TRIG0_Pos                (4UL)                     /*!< TRIG0 (Bit 4)                                         */
#define PWM_SYNC_TRIG0_Msk                (0x10UL)                  /*!< TRIG0 (Bitfield-Mask: 0x01)                           */
#define PWM_SYNC_TRIG1_Pos                (5UL)                     /*!< TRIG1 (Bit 5)                                         */
#define PWM_SYNC_TRIG1_Msk                (0x20UL)                  /*!< TRIG1 (Bitfield-Mask: 0x01)                           */
#define PWM_SYNC_TRIG2_Pos                (6UL)                     /*!< TRIG2 (Bit 6)                                         */
#define PWM_SYNC_TRIG2_Msk                (0x40UL)                  /*!< TRIG2 (Bitfield-Mask: 0x01)                           */
#define PWM_SYNC_SWSYNC_Pos               (7UL)                     /*!< SWSYNC (Bit 7)                                        */
#define PWM_SYNC_SWSYNC_Msk               (0x80UL)                  /*!< SWSYNC (Bitfield-Mask: 0x01)                          */
#define PWM_SYNC_SYNCPOL_Pos              (11UL)                    /*!< SYNCPOL (Bit 11)                                      */
#define PWM_SYNC_SYNCPOL_Msk              (0x800UL)                 /*!< SYNCPOL (Bitfield-Mask: 0x01)                         */
/* ========================================================  OUTINIT  ======================================================== */
#define PWM_OUTINIT_CH0OIV_Pos            (0UL)                     /*!< CH0OIV (Bit 0)                                        */
#define PWM_OUTINIT_CH0OIV_Msk            (0x1UL)                   /*!< CH0OIV (Bitfield-Mask: 0x01)                          */
#define PWM_OUTINIT_CH1OIV_Pos            (1UL)                     /*!< CH1OIV (Bit 1)                                        */
#define PWM_OUTINIT_CH1OIV_Msk            (0x2UL)                   /*!< CH1OIV (Bitfield-Mask: 0x01)                          */
#define PWM_OUTINIT_CH2OIV_Pos            (2UL)                     /*!< CH2OIV (Bit 2)                                        */
#define PWM_OUTINIT_CH2OIV_Msk            (0x4UL)                   /*!< CH2OIV (Bitfield-Mask: 0x01)                          */
#define PWM_OUTINIT_CH3OIV_Pos            (3UL)                     /*!< CH3OIV (Bit 3)                                        */
#define PWM_OUTINIT_CH3OIV_Msk            (0x8UL)                   /*!< CH3OIV (Bitfield-Mask: 0x01)                          */
#define PWM_OUTINIT_CH4OIV_Pos            (4UL)                     /*!< CH4OIV (Bit 4)                                        */
#define PWM_OUTINIT_CH4OIV_Msk            (0x10UL)                  /*!< CH4OIV (Bitfield-Mask: 0x01)                          */
#define PWM_OUTINIT_CH5OIV_Pos            (5UL)                     /*!< CH5OIV (Bit 5)                                        */
#define PWM_OUTINIT_CH5OIV_Msk            (0x20UL)                  /*!< CH5OIV (Bitfield-Mask: 0x01)                          */
#define PWM_OUTINIT_CH6OIV_Pos            (6UL)                     /*!< CH6OIV (Bit 6)                                        */
#define PWM_OUTINIT_CH6OIV_Msk            (0x40UL)                  /*!< CH6OIV (Bitfield-Mask: 0x01)                          */
#define PWM_OUTINIT_CH7OIV_Pos            (7UL)                     /*!< CH7OIV (Bit 7)                                        */
#define PWM_OUTINIT_CH7OIV_Msk            (0x80UL)                  /*!< CH7OIV (Bitfield-Mask: 0x01)                          */
#define PWM_OUTINIT_CHOIV_Msk             (0xffUL)                  /*!< CH7IV  (Bitfield-Mask: 0xff)                          */
/* =========================================================  OMCR  ========================================================== */
#define PWM_OMCR_CH0OMEN_Pos              (0UL)                     /*!< CH0OMEN (Bit 0)                                       */
#define PWM_OMCR_CH0OMEN_Msk              (0x1UL)                   /*!< CH0OMEN (Bitfield-Mask: 0x01)                         */
#define PWM_OMCR_CH1OMEN_Pos              (1UL)                     /*!< CH1OMEN (Bit 1)                                       */
#define PWM_OMCR_CH1OMEN_Msk              (0x2UL)                   /*!< CH1OMEN (Bitfield-Mask: 0x01)                         */
#define PWM_OMCR_CH2OMEN_Pos              (2UL)                     /*!< CH2OMEN (Bit 2)                                       */
#define PWM_OMCR_CH2OMEN_Msk              (0x4UL)                   /*!< CH2OMEN (Bitfield-Mask: 0x01)                         */
#define PWM_OMCR_CH3OMEN_Pos              (3UL)                     /*!< CH3OMEN (Bit 3)                                       */
#define PWM_OMCR_CH3OMEN_Msk              (0x8UL)                   /*!< CH3OMEN (Bitfield-Mask: 0x01)                         */
#define PWM_OMCR_CH4OMEN_Pos              (4UL)                     /*!< CH4OMEN (Bit 4)                                       */
#define PWM_OMCR_CH4OMEN_Msk              (0x10UL)                  /*!< CH4OMEN (Bitfield-Mask: 0x01)                         */
#define PWM_OMCR_CH5OMEN_Pos              (5UL)                     /*!< CH5OMEN (Bit 5)                                       */
#define PWM_OMCR_CH5OMEN_Msk              (0x20UL)                  /*!< CH5OMEN (Bitfield-Mask: 0x01)                         */
#define PWM_OMCR_CH6OMEN_Pos              (6UL)                     /*!< CH6OMEN (Bit 6)                                       */
#define PWM_OMCR_CH6OMEN_Msk              (0x40UL)                  /*!< CH6OMEN (Bitfield-Mask: 0x01)                         */
#define PWM_OMCR_CH7OMEN_Pos              (7UL)                     /*!< CH7OMEN (Bit 7)                                       */
#define PWM_OMCR_CH7OMEN_Msk              (0x80UL)                  /*!< CH7OMEN (Bitfield-Mask: 0x01)                         */
#define PWM_OMCR_CHOMEN_Msk               (0xffUL)                  /*!< CHOMEN  (Bitfield-Mask: 0xff)                         */
/* ========================================================  MODESEL  ======================================================== */
#define PWM_MODESEL_PAIR0COMBINEN_Pos     (0UL)                     /*!< PAIR0COMBINEN (Bit 0)                                 */
#define PWM_MODESEL_PAIR0COMBINEN_Msk     (0x1UL)                   /*!< PAIR0COMBINEN (Bitfield-Mask: 0x01)                   */
#define PWM_MODESEL_PAIR0COMPEN_Pos       (1UL)                     /*!< PAIR0COMPEN (Bit 1)                                   */
#define PWM_MODESEL_PAIR0COMPEN_Msk       (0x2UL)                   /*!< PAIR0COMPEN (Bitfield-Mask: 0x01)                     */
#define PWM_MODESEL_PAIR0DECAPEN_Pos      (2UL)                     /*!< PAIR0DECAPEN (Bit 2)                                  */
#define PWM_MODESEL_PAIR0DECAPEN_Msk      (0x4UL)                   /*!< PAIR0DECAPEN (Bitfield-Mask: 0x01)                    */
#define PWM_MODESEL_PAIR0DECAP_Pos        (3UL)                     /*!< PAIR0DECAP (Bit 3)                                    */
#define PWM_MODESEL_PAIR0DECAP_Msk        (0x8UL)                   /*!< PAIR0DECAP (Bitfield-Mask: 0x01)                      */
#define PWM_MODESEL_PAIR0DTEN_Pos         (4UL)                     /*!< PAIR0DTEN (Bit 4)                                     */
#define PWM_MODESEL_PAIR0DTEN_Msk         (0x10UL)                  /*!< PAIR0DTEN (Bitfield-Mask: 0x01)                       */
#define PWM_MODESEL_PAIR0SYNCEN_Pos       (5UL)                     /*!< PAIR0SYNCEN (Bit 5)                                   */
#define PWM_MODESEL_PAIR0SYNCEN_Msk       (0x20UL)                  /*!< PAIR0SYNCEN (Bitfield-Mask: 0x01)                     */
#define PWM_MODESEL_PAIR0FAULTEN_Pos      (6UL)                     /*!< PAIR0FAULTEN (Bit 6)                                  */
#define PWM_MODESEL_PAIR0FAULTEN_Msk      (0x40UL)                  /*!< PAIR0FAULTEN (Bitfield-Mask: 0x01)                    */
#define PWM_MODESEL_PAIR1COMBINEN_Pos     (8UL)                     /*!< PAIR1COMBINEN (Bit 8)                                 */
#define PWM_MODESEL_PAIR1COMBINEN_Msk     (0x100UL)                 /*!< PAIR1COMBINEN (Bitfield-Mask: 0x01)                   */
#define PWM_MODESEL_PAIR1COMPEN_Pos       (9UL)                     /*!< PAIR1COMPEN (Bit 9)                                   */
#define PWM_MODESEL_PAIR1COMPEN_Msk       (0x200UL)                 /*!< PAIR1COMPEN (Bitfield-Mask: 0x01)                     */
#define PWM_MODESEL_PAIR1DECAPEN_Pos      (10UL)                    /*!< PAIR1DECAPEN (Bit 10)                                 */
#define PWM_MODESEL_PAIR1DECAPEN_Msk      (0x400UL)                 /*!< PAIR1DECAPEN (Bitfield-Mask: 0x01)                    */
#define PWM_MODESEL_PAIR1DECAP_Pos        (11UL)                    /*!< PAIR1DECAP (Bit 11)                                   */
#define PWM_MODESEL_PAIR1DECAP_Msk        (0x800UL)                 /*!< PAIR1DECAP (Bitfield-Mask: 0x01)                      */
#define PWM_MODESEL_PAIR1DTEN_Pos         (12UL)                    /*!< PAIR1DTEN (Bit 12)                                    */
#define PWM_MODESEL_PAIR1DTEN_Msk         (0x1000UL)                /*!< PAIR1DTEN (Bitfield-Mask: 0x01)                       */
#define PWM_MODESEL_PAIR1SYNCEN_Pos       (13UL)                    /*!< PAIR1SYNCEN (Bit 13)                                  */
#define PWM_MODESEL_PAIR1SYNCEN_Msk       (0x2000UL)                /*!< PAIR1SYNCEN (Bitfield-Mask: 0x01)                     */
#define PWM_MODESEL_PAIR1FAULTEN_Pos      (14UL)                    /*!< PAIR1FAULTEN (Bit 14)                                 */
#define PWM_MODESEL_PAIR1FAULTEN_Msk      (0x4000UL)                /*!< PAIR1FAULTEN (Bitfield-Mask: 0x01)                    */
#define PWM_MODESEL_PAIR2COMBINEN_Pos     (16UL)                    /*!< PAIR2COMBINEN (Bit 16)                                */
#define PWM_MODESEL_PAIR2COMBINEN_Msk     (0x10000UL)               /*!< PAIR2COMBINEN (Bitfield-Mask: 0x01)                   */
#define PWM_MODESEL_PAIR2COMPEN_Pos       (17UL)                    /*!< PAIR2COMPEN (Bit 17)                                  */
#define PWM_MODESEL_PAIR2COMPEN_Msk       (0x20000UL)               /*!< PAIR2COMPEN (Bitfield-Mask: 0x01)                     */
#define PWM_MODESEL_PAIR2DECAPEN_Pos      (18UL)                    /*!< PAIR2DECAPEN (Bit 18)                                 */
#define PWM_MODESEL_PAIR2DECAPEN_Msk      (0x40000UL)               /*!< PAIR2DECAPEN (Bitfield-Mask: 0x01)                    */
#define PWM_MODESEL_PAIR2DECAP_Pos        (19UL)                    /*!< PAIR2DECAP (Bit 19)                                   */
#define PWM_MODESEL_PAIR2DECAP_Msk        (0x80000UL)               /*!< PAIR2DECAP (Bitfield-Mask: 0x01)                      */
#define PWM_MODESEL_PAIR2DTEN_Pos         (20UL)                    /*!< PAIR2DTEN (Bit 20)                                    */
#define PWM_MODESEL_PAIR2DTEN_Msk         (0x100000UL)              /*!< PAIR2DTEN (Bitfield-Mask: 0x01)                       */
#define PWM_MODESEL_PAIR2SYNCEN_Pos       (21UL)                    /*!< PAIR2SYNCEN (Bit 21)                                  */
#define PWM_MODESEL_PAIR2SYNCEN_Msk       (0x200000UL)              /*!< PAIR2SYNCEN (Bitfield-Mask: 0x01)                     */
#define PWM_MODESEL_PAIR2FAULTEN_Pos      (22UL)                    /*!< PAIR2FAULTEN (Bit 22)                                 */
#define PWM_MODESEL_PAIR2FAULTEN_Msk      (0x400000UL)              /*!< PAIR2FAULTEN (Bitfield-Mask: 0x01)                    */
#define PWM_MODESEL_PAIR3COMBINEN_Pos     (24UL)                    /*!< PAIR3COMBINEN (Bit 24)                                */
#define PWM_MODESEL_PAIR3COMBINEN_Msk     (0x1000000UL)             /*!< PAIR3COMBINEN (Bitfield-Mask: 0x01)                   */
#define PWM_MODESEL_PAIR3COMPEN_Pos       (25UL)                    /*!< PAIR3COMPEN (Bit 25)                                  */
#define PWM_MODESEL_PAIR3COMPEN_Msk       (0x2000000UL)             /*!< PAIR3COMPEN (Bitfield-Mask: 0x01)                     */
#define PWM_MODESEL_PAIR3DECAPEN_Pos      (26UL)                    /*!< PAIR3DECAPEN (Bit 26)                                 */
#define PWM_MODESEL_PAIR3DECAPEN_Msk      (0x4000000UL)             /*!< PAIR3DECAPEN (Bitfield-Mask: 0x01)                    */
#define PWM_MODESEL_PAIR3DECAP_Pos        (27UL)                    /*!< PAIR3DECAP (Bit 27)                                   */
#define PWM_MODESEL_PAIR3DECAP_Msk        (0x8000000UL)             /*!< PAIR3DECAP (Bitfield-Mask: 0x01)                      */
#define PWM_MODESEL_PAIR3DTEN_Pos         (28UL)                    /*!< PAIR3DTEN (Bit 28)                                    */
#define PWM_MODESEL_PAIR3DTEN_Msk         (0x10000000UL)            /*!< PAIR3DTEN (Bitfield-Mask: 0x01)                       */
#define PWM_MODESEL_PAIR3SYNCEN_Pos       (29UL)                    /*!< PAIR3SYNCEN (Bit 29)                                  */
#define PWM_MODESEL_PAIR3SYNCEN_Msk       (0x20000000UL)            /*!< PAIR3SYNCEN (Bitfield-Mask: 0x01)                     */
#define PWM_MODESEL_PAIR3FAULTEN_Pos      (30UL)                    /*!< PAIR3FAULTEN (Bit 30)                                 */
#define PWM_MODESEL_PAIR3FAULTEN_Msk      (0x40000000UL)            /*!< PAIR3FAULTEN (Bitfield-Mask: 0x01)                    */
#define PWM_MODESEL_PAIR_CONFIG_WIDTH     (8UL)                     /*!< PAIRCONFIG                                            */
/* =========================================================  DTSET  ========================================================= */
#define PWM_DTSET_DTVAL_Pos               (0UL)                     /*!< DTVAL (Bit 0)                                         */
#define PWM_DTSET_DTVAL_Msk               (0x3fUL)                  /*!< DTVAL (Bitfield-Mask: 0x3f)                           */
#define PWM_DTSET_DTPSC_Pos               (6UL)                     /*!< DTPSC (Bit 6)                                         */
#define PWM_DTSET_DTPSC_Msk               (0xc0UL)                  /*!< DTPSC (Bitfield-Mask: 0x03)                           */
/* ========================================================  EXTTRIG  ======================================================== */
#define PWM_EXTTRIG_CH0TRIG_Pos           (0UL)                     /*!< CH0TRIG (Bit 0)                                       */
#define PWM_EXTTRIG_CH0TRIG_Msk           (0x1UL)                   /*!< CH0TRIG (Bitfield-Mask: 0x01)                         */
#define PWM_EXTTRIG_CH1TRIG_Pos           (1UL)                     /*!< CH1TRIG (Bit 1)                                       */
#define PWM_EXTTRIG_CH1TRIG_Msk           (0x2UL)                   /*!< CH1TRIG (Bitfield-Mask: 0x01)                         */
#define PWM_EXTTRIG_CH2TRIG_Pos           (2UL)                     /*!< CH2TRIG (Bit 2)                                       */
#define PWM_EXTTRIG_CH2TRIG_Msk           (0x4UL)                   /*!< CH2TRIG (Bitfield-Mask: 0x01)                         */
#define PWM_EXTTRIG_CH3TRIG_Pos           (3UL)                     /*!< CH3TRIG (Bit 3)                                       */
#define PWM_EXTTRIG_CH3TRIG_Msk           (0x8UL)                   /*!< CH3TRIG (Bitfield-Mask: 0x01)                         */
#define PWM_EXTTRIG_CH4TRIG_Pos           (4UL)                     /*!< CH4TRIG (Bit 4)                                       */
#define PWM_EXTTRIG_CH4TRIG_Msk           (0x10UL)                  /*!< CH4TRIG (Bitfield-Mask: 0x01)                         */
#define PWM_EXTTRIG_CH5TRIG_Pos           (5UL)                     /*!< CH5TRIG (Bit 5)                                       */
#define PWM_EXTTRIG_CH5TRIG_Msk           (0x20UL)                  /*!< CH5TRIG (Bitfield-Mask: 0x01)                         */
#define PWM_EXTTRIG_CH6TRIG_Pos           (6UL)                     /*!< CH6TRIG (Bit 6)                                       */
#define PWM_EXTTRIG_CH6TRIG_Msk           (0x40UL)                  /*!< CH6TRIG (Bitfield-Mask: 0x01)                         */
#define PWM_EXTTRIG_CH7TRIG_Pos           (7UL)                     /*!< CH7TRIG (Bit 7)                                       */
#define PWM_EXTTRIG_CH7TRIG_Msk           (0x80UL)                  /*!< CH7TRIG (Bitfield-Mask: 0x01)                         */
#define PWM_EXTTRIG_INITTRIGEN_Pos        (8UL)                     /*!< INITTRIGEN (Bit 8)                                    */
#define PWM_EXTTRIG_INITTRIGEN_Msk        (0x100UL)                 /*!< INITTRIGEN (Bitfield-Mask: 0x01)                      */
#define PWM_EXTTRIG_TRIGF_Pos             (9UL)                     /*!< TRIGF (Bit 9)                                         */
#define PWM_EXTTRIG_TRIGF_Msk             (0x200UL)                 /*!< TRIGF (Bitfield-Mask: 0x01)                           */
/* =======================================================  CHOPOLCR  ======================================================== */
#define PWM_CHOPOLCR_CH0POL_Pos           (0UL)                     /*!< CH0POL (Bit 0)                                        */
#define PWM_CHOPOLCR_CH0POL_Msk           (0x1UL)                   /*!< CH0POL (Bitfield-Mask: 0x01)                          */
#define PWM_CHOPOLCR_CH1POL_Pos           (1UL)                     /*!< CH1POL (Bit 1)                                        */
#define PWM_CHOPOLCR_CH1POL_Msk           (0x2UL)                   /*!< CH1POL (Bitfield-Mask: 0x01)                          */
#define PWM_CHOPOLCR_CH2POL_Pos           (2UL)                     /*!< CH2POL (Bit 2)                                        */
#define PWM_CHOPOLCR_CH2POL_Msk           (0x4UL)                   /*!< CH2POL (Bitfield-Mask: 0x01)                          */
#define PWM_CHOPOLCR_CH3POL_Pos           (3UL)                     /*!< CH3POL (Bit 3)                                        */
#define PWM_CHOPOLCR_CH3POL_Msk           (0x8UL)                   /*!< CH3POL (Bitfield-Mask: 0x01)                          */
#define PWM_CHOPOLCR_CH4POL_Pos           (4UL)                     /*!< CH4POL (Bit 4)                                        */
#define PWM_CHOPOLCR_CH4POL_Msk           (0x10UL)                  /*!< CH4POL (Bitfield-Mask: 0x01)                          */
#define PWM_CHOPOLCR_CH5POL_Pos           (5UL)                     /*!< CH5POL (Bit 5)                                        */
#define PWM_CHOPOLCR_CH5POL_Msk           (0x20UL)                  /*!< CH5POL (Bitfield-Mask: 0x01)                          */
#define PWM_CHOPOLCR_CH6POL_Pos           (6UL)                     /*!< CH6POL (Bit 6)                                        */
#define PWM_CHOPOLCR_CH6POL_Msk           (0x40UL)                  /*!< CH6POL (Bitfield-Mask: 0x01)                          */
#define PWM_CHOPOLCR_CH7POL_Pos           (7UL)                     /*!< CH7POL (Bit 7)                                        */
#define PWM_CHOPOLCR_CH7POL_Msk           (0x80UL)                  /*!< CH7POL (Bitfield-Mask: 0x01)                          */
/* =========================================================  FDSR  ========================================================== */
#define PWM_FDSR_FAULTDF0_Pos             (0UL)                     /*!< FAULTDF0 (Bit 0)                                      */
#define PWM_FDSR_FAULTDF0_Msk             (0x1UL)                   /*!< FAULTDF0 (Bitfield-Mask: 0x01)                        */
#define PWM_FDSR_FAULTDF1_Pos             (1UL)                     /*!< FAULTDF1 (Bit 1)                                      */
#define PWM_FDSR_FAULTDF1_Msk             (0x2UL)                   /*!< FAULTDF1 (Bitfield-Mask: 0x01)                        */
#define PWM_FDSR_FAULTDF2_Pos             (2UL)                     /*!< FAULTDF2 (Bit 2)                                      */
#define PWM_FDSR_FAULTDF2_Msk             (0x4UL)                   /*!< FAULTDF2 (Bitfield-Mask: 0x01)                        */
#define PWM_FDSR_FAULTIN_Pos              (5UL)                     /*!< FAULTIN (Bit 5)                                       */
#define PWM_FDSR_FAULTIN_Msk              (0x20UL)                  /*!< FAULTIN (Bitfield-Mask: 0x01)                         */
#define PWM_FDSR_WPEN_Pos                 (6UL)                     /*!< WPEN (Bit 6)                                          */
#define PWM_FDSR_WPEN_Msk                 (0x40UL)                  /*!< WPEN (Bitfield-Mask: 0x01)                            */
#define PWM_FDSR_FAULTDF_Pos              (7UL)                     /*!< FAULTDF (Bit 7)                                       */
#define PWM_FDSR_FAULTDF_Msk              (0x80UL)                  /*!< FAULTDF (Bitfield-Mask: 0x01)                         */
/* =======================================================  CAPFILTER  ======================================================= */
#define PWM_CAPFILTER_CH0CAPFVAL_Pos      (0UL)                     /*!< CH0CAPFVAL (Bit 0)                                    */
#define PWM_CAPFILTER_CH0CAPFVAL_Msk      (0x1fUL)                  /*!< CH0CAPFVAL (Bitfield-Mask: 0x1f)                      */
#define PWM_CAPFILTER_CH1CAPFVAL_Pos      (5UL)                     /*!< CH1CAPFVAL (Bit 5)                                    */
#define PWM_CAPFILTER_CH1CAPFVAL_Msk      (0x3e0UL)                 /*!< CH1CAPFVAL (Bitfield-Mask: 0x1f)                      */
#define PWM_CAPFILTER_CH2CAPFVAL_Pos      (10UL)                    /*!< CH2CAPFVAL (Bit 10)                                   */
#define PWM_CAPFILTER_CH2CAPFVAL_Msk      (0x7c00UL)                /*!< CH2CAPFVAL (Bitfield-Mask: 0x1f)                      */
#define PWM_CAPFILTER_CH3CAPFVAL_Pos      (15UL)                    /*!< CH3CAPFVAL (Bit 15)                                   */
#define PWM_CAPFILTER_CH3CAPFVAL_Msk      (0xf8000UL)               /*!< CH3CAPFVAL (Bitfield-Mask: 0x1f)                      */
#define PWM_CAPFILTER_CHCAPFVAL_WIDTH     (5UL)                     /*!< CHCAPFVAL  (Bitfield-Mask: 0x1f)                      */
/* ========================================================  FFAFER  ========================================================= */
#define PWM_FFAFER_FER0EN_Pos             (0UL)                     /*!< FER0EN (Bit 0)                                        */
#define PWM_FFAFER_FER0EN_Msk             (0x1UL)                   /*!< FER0EN (Bitfield-Mask: 0x01)                          */
#define PWM_FFAFER_FER1EN_Pos             (1UL)                     /*!< FER1EN (Bit 1)                                        */
#define PWM_FFAFER_FER1EN_Msk             (0x2UL)                   /*!< FER1EN (Bitfield-Mask: 0x01)                          */
#define PWM_FFAFER_FER2EN_Pos             (2UL)                     /*!< FER2EN (Bit 2)                                        */
#define PWM_FFAFER_FER2EN_Msk             (0x4UL)                   /*!< FER2EN (Bitfield-Mask: 0x01)                          */
#define PWM_FFAFER_FF0EN_Pos              (4UL)                     /*!< FF0EN (Bit 4)                                         */
#define PWM_FFAFER_FF0EN_Msk              (0x10UL)                  /*!< FF0EN (Bitfield-Mask: 0x01)                           */
#define PWM_FFAFER_FF1EN_Pos              (5UL)                     /*!< FF1EN (Bit 5)                                         */
#define PWM_FFAFER_FF1EN_Msk              (0x20UL)                  /*!< FF1EN (Bitfield-Mask: 0x01)                           */
#define PWM_FFAFER_FF2EN_Pos              (6UL)                     /*!< FF2EN (Bit 6)                                         */
#define PWM_FFAFER_FF2EN_Msk              (0x40UL)                  /*!< FF2EN (Bitfield-Mask: 0x01)                           */
#define PWM_FFAFER_FFVAL_Pos              (8UL)                     /*!< FFVAL (Bit 8)                                         */
#define PWM_FFAFER_FFVAL_Msk              (0xff00UL)                /*!< FFVAL (Bitfield-Mask: 0xff)                           */
/* ==========================================================  QDI  ========================================================== */
#define PWM_QDI_QDIEN_Pos                 (0UL)                     /*!< QDIEN (Bit 0)                                         */
#define PWM_QDI_QDIEN_Msk                 (0x1UL)                   /*!< QDIEN (Bitfield-Mask: 0x01)                           */
#define PWM_QDI_CNTOFDIR_Pos              (1UL)                     /*!< CNTOFDIR (Bit 1)                                      */
#define PWM_QDI_CNTOFDIR_Msk              (0x2UL)                   /*!< CNTOFDIR (Bitfield-Mask: 0x01)                        */
#define PWM_QDI_QUADIR_Pos                (2UL)                     /*!< QUADIR (Bit 2)                                        */
#define PWM_QDI_QUADIR_Msk                (0x4UL)                   /*!< QUADIR (Bitfield-Mask: 0x01)                          */
#define PWM_QDI_QUADMODE_Pos              (3UL)                     /*!< QUADMODE (Bit 3)                                      */
#define PWM_QDI_QUADMODE_Msk              (0x8UL)                   /*!< QUADMODE (Bitfield-Mask: 0x01)                        */
#define PWM_QDI_PHBPOL_Pos                (4UL)                     /*!< PHBPOL (Bit 4)                                        */
#define PWM_QDI_PHBPOL_Msk                (0x10UL)                  /*!< PHBPOL (Bitfield-Mask: 0x01)                          */
#define PWM_QDI_PHAPOL_Pos                (5UL)                     /*!< PHAPOL (Bit 5)                                        */
#define PWM_QDI_PHAPOL_Msk                (0x20UL)                  /*!< PHAPOL (Bitfield-Mask: 0x01)                          */
/* =========================================================  CONF  ========================================================== */
#define PWM_CONF_CNTOFNUM_Pos             (0UL)                     /*!< CNTOFNUM (Bit 0)                                      */
#define PWM_CONF_CNTOFNUM_Msk             (0x7fUL)                  /*!< CNTOFNUM (Bitfield-Mask: 0x7f)                        */
#define PWM_CONF_GTBEEN_Pos               (9UL)                     /*!< GTBEEN (Bit 9)                                        */
#define PWM_CONF_GTBEEN_Msk               (0x200UL)                 /*!< GTBEEN (Bitfield-Mask: 0x01)                          */
#define PWM_CONF_GTBEOUT_Pos              (10UL)                    /*!< GTBEOUT (Bit 10)                                      */
#define PWM_CONF_GTBEOUT_Msk              (0x400UL)                 /*!< GTBEOUT (Bitfield-Mask: 0x01)                         */
#define PWM_CONF_EVENT0PSC_Pos            (16UL)                    /*!< EVENT0PSC (Bit 16)                                    */
#define PWM_CONF_EVENT0PSC_Msk            (0x30000UL)               /*!< EVENT0PSC (Bitfield-Mask: 0x03)                       */
#define PWM_CONF_EVENT1PSC_Pos            (18UL)                    /*!< EVENT1PSC (Bit 18)                                    */
#define PWM_CONF_EVENT1PSC_Msk            (0xc0000UL)               /*!< EVENT1PSC (Bitfield-Mask: 0x03)                       */
#define PWM_CONF_EVENT2PSC_Pos            (20UL)                    /*!< EVENT2PSC (Bit 20)                                    */
#define PWM_CONF_EVENT2PSC_Msk            (0x300000UL)              /*!< EVENT2PSC (Bitfield-Mask: 0x03)                       */
#define PWM_CONF_EVENT3PSC_Pos            (22UL)                    /*!< EVENT3PSC (Bit 22)                                    */
#define PWM_CONF_EVENT3PSC_Msk            (0xc00000UL)              /*!< EVENT3PSC (Bitfield-Mask: 0x03)                       */
#define PWM_CONF_EVENT4PSC_Pos            (24UL)                    /*!< EVENT4PSC (Bit 24)                                    */
#define PWM_CONF_EVENT4PSC_Msk            (0x3000000UL)             /*!< EVENT4PSC (Bitfield-Mask: 0x03)                       */
#define PWM_CONF_EVENT5PSC_Pos            (26UL)                    /*!< EVENT5PSC (Bit 26)                                    */
#define PWM_CONF_EVENT5PSC_Msk            (0xc000000UL)             /*!< EVENT5PSC (Bitfield-Mask: 0x03)                       */
#define PWM_CONF_EVENT6PSC_Pos            (28UL)                    /*!< EVENT6PSC (Bit 28)                                    */
#define PWM_CONF_EVENT6PSC_Msk            (0x30000000UL)            /*!< EVENT6PSC (Bitfield-Mask: 0x03)                       */
#define PWM_CONF_EVENT7PSC_Pos            (30UL)                    /*!< EVENT7PSC (Bit 30)                                    */
#define PWM_CONF_EVENT7PSC_Msk            (0xc0000000UL)            /*!< EVENT7PSC (Bitfield-Mask: 0x03)                       */
#define PWM_CONF_EVENTPSC_WIDTH           (2UL)                     /*!< EVENTPSC (Bitfield-Mask: 0x03)                        */
/* ========================================================  FLTPOL  ========================================================= */
#define PWM_FLTPOL_FLT0POL_Pos            (0UL)                     /*!< FLT0POL (Bit 0)                                       */
#define PWM_FLTPOL_FLT0POL_Msk            (0x1UL)                   /*!< FLT0POL (Bitfield-Mask: 0x01)                         */
#define PWM_FLTPOL_FLT1POL_Pos            (1UL)                     /*!< FLT1POL (Bit 1)                                       */
#define PWM_FLTPOL_FLT1POL_Msk            (0x2UL)                   /*!< FLT1POL (Bitfield-Mask: 0x01)                         */
#define PWM_FLTPOL_FLT2POL_Pos            (2UL)                     /*!< FLT2POL (Bit 2)                                       */
#define PWM_FLTPOL_FLT2POL_Msk            (0x4UL)                   /*!< FLT2POL (Bitfield-Mask: 0x01)                         */
/* ========================================================  SYNCONF  ======================================================== */
#define PWM_SYNCONF_HWTRIGMODESEL_Pos     (0UL)                     /*!< HWTRIGMODESEL (Bit 0)                                 */
#define PWM_SYNCONF_HWTRIGMODESEL_Msk     (0x1UL)                   /*!< HWTRIGMODESEL (Bitfield-Mask: 0x01)                   */
#define PWM_SYNCONF_CNTINC_Pos            (2UL)                     /*!< CNTINC (Bit 2)                                        */
#define PWM_SYNCONF_CNTINC_Msk            (0x4UL)                   /*!< CNTINC (Bitfield-Mask: 0x01)                          */
#define PWM_SYNCONF_INVC_Pos              (4UL)                     /*!< INVC (Bit 4)                                          */
#define PWM_SYNCONF_INVC_Msk              (0x10UL)                  /*!< INVC (Bitfield-Mask: 0x01)                            */
#define PWM_SYNCONF_SWOC_Pos              (5UL)                     /*!< SWOC (Bit 5)                                          */
#define PWM_SYNCONF_SWOC_Msk              (0x20UL)                  /*!< SWOC (Bitfield-Mask: 0x01)                            */
#define PWM_SYNCONF_SYNCMODE_Pos          (7UL)                     /*!< SYNCMODE (Bit 7)                                      */
#define PWM_SYNCONF_SYNCMODE_Msk          (0x80UL)                  /*!< SYNCMODE (Bitfield-Mask: 0x01)                        */
#define PWM_SYNCONF_CNTVSWSYNC_Pos        (8UL)                     /*!< CNTVSWSYNC (Bit 8)                                    */
#define PWM_SYNCONF_CNTVSWSYNC_Msk        (0x100UL)                 /*!< CNTVSWSYNC (Bitfield-Mask: 0x01)                      */
#define PWM_SYNCONF_PWMSVSWSYNC_Pos       (9UL)                     /*!< PWMSVSWSYNC (Bit 9)                                   */
#define PWM_SYNCONF_PWMSVSWSYNC_Msk       (0x200UL)                 /*!< PWMSVSWSYNC (Bitfield-Mask: 0x01)                     */
#define PWM_SYNCONF_OMVSWSYNC_Pos         (10UL)                    /*!< OMVSWSYNC (Bit 10)                                    */
#define PWM_SYNCONF_OMVSWSYNC_Msk         (0x400UL)                 /*!< OMVSWSYNC (Bitfield-Mask: 0x01)                       */
#define PWM_SYNCONF_INVSWSYNC_Pos         (11UL)                    /*!< INVSWSYNC (Bit 11)                                    */
#define PWM_SYNCONF_INVSWSYNC_Msk         (0x800UL)                 /*!< INVSWSYNC (Bitfield-Mask: 0x01)                       */
#define PWM_SYNCONF_SWVSWSYNC_Pos         (12UL)                    /*!< SWVSWSYNC (Bit 12)                                    */
#define PWM_SYNCONF_SWVSWSYNC_Msk         (0x1000UL)                /*!< SWVSWSYNC (Bitfield-Mask: 0x01)                       */
#define PWM_SYNCONF_CNTVHWSYNC_Pos        (16UL)                    /*!< CNTVHWSYNC (Bit 16)                                   */
#define PWM_SYNCONF_CNTVHWSYNC_Msk        (0x10000UL)               /*!< CNTVHWSYNC (Bitfield-Mask: 0x01)                      */
#define PWM_SYNCONF_PWMSVHWSYNC_Pos       (17UL)                    /*!< PWMSVHWSYNC (Bit 17)                                  */
#define PWM_SYNCONF_PWMSVHWSYNC_Msk       (0x20000UL)               /*!< PWMSVHWSYNC (Bitfield-Mask: 0x01)                     */
#define PWM_SYNCONF_OMVHWSYNC_Pos         (18UL)                    /*!< OMVHWSYNC (Bit 18)                                    */
#define PWM_SYNCONF_OMVHWSYNC_Msk         (0x40000UL)               /*!< OMVHWSYNC (Bitfield-Mask: 0x01)                       */
#define PWM_SYNCONF_INVHWSYNC_Pos         (19UL)                    /*!< INVHWSYNC (Bit 19)                                    */
#define PWM_SYNCONF_INVHWSYNC_Msk         (0x80000UL)               /*!< INVHWSYNC (Bitfield-Mask: 0x01)                       */
#define PWM_SYNCONF_SWVHWSYNC_Pos         (20UL)                    /*!< SWVHWSYNC (Bit 20)                                    */
#define PWM_SYNCONF_SWVHWSYNC_Msk         (0x100000UL)              /*!< SWVHWSYNC (Bitfield-Mask: 0x01)                       */
#define PWM_SYNCONF_SWPOL_Pos             (21UL)                    /*!< SWPOL (Bit 21)                                        */
#define PWM_SYNCONF_SWPOL_Msk             (0x200000UL)              /*!< SWPOL (Bitfield-Mask: 0x01)                           */
#define PWM_SYNCONF_HWPOL_Pos             (22UL)                    /*!< HWPOL (Bit 22)                                        */
#define PWM_SYNCONF_HWPOL_Msk             (0x400000UL)              /*!< HWPOL (Bitfield-Mask: 0x01)                           */
/* =========================================================  INVCR  ========================================================= */
#define PWM_INVCR_PAIR0INVEN_Pos          (0UL)                     /*!< PAIR0INVEN (Bit 0)                                    */
#define PWM_INVCR_PAIR0INVEN_Msk          (0x1UL)                   /*!< PAIR0INVEN (Bitfield-Mask: 0x01)                      */
#define PWM_INVCR_PAIR1INVEN_Pos          (1UL)                     /*!< PAIR1INVEN (Bit 1)                                    */
#define PWM_INVCR_PAIR1INVEN_Msk          (0x2UL)                   /*!< PAIR1INVEN (Bitfield-Mask: 0x01)                      */
#define PWM_INVCR_PAIR2INVEN_Pos          (2UL)                     /*!< PAIR2INVEN (Bit 2)                                    */
#define PWM_INVCR_PAIR2INVEN_Msk          (0x4UL)                   /*!< PAIR2INVEN (Bitfield-Mask: 0x01)                      */
#define PWM_INVCR_PAIR3INVEN_Pos          (3UL)                     /*!< PAIR3INVEN (Bit 3)                                    */
#define PWM_INVCR_PAIR3INVEN_Msk          (0x8UL)                   /*!< PAIR3INVEN (Bitfield-Mask: 0x01)                      */
/* ========================================================  CHOSWCR  ======================================================== */
#define PWM_CHOSWCR_CH0SWEN_Pos           (0UL)                     /*!< CH0SWEN (Bit 0)                                       */
#define PWM_CHOSWCR_CH0SWEN_Msk           (0x1UL)                   /*!< CH0SWEN (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CH1SWEN_Pos           (1UL)                     /*!< CH1SWEN (Bit 1)                                       */
#define PWM_CHOSWCR_CH1SWEN_Msk           (0x2UL)                   /*!< CH1SWEN (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CH2SWEN_Pos           (2UL)                     /*!< CH2SWEN (Bit 2)                                       */
#define PWM_CHOSWCR_CH2SWEN_Msk           (0x4UL)                   /*!< CH2SWEN (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CH3SWEN_Pos           (3UL)                     /*!< CH3SWEN (Bit 3)                                       */
#define PWM_CHOSWCR_CH3SWEN_Msk           (0x8UL)                   /*!< CH3SWEN (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CH4SWEN_Pos           (4UL)                     /*!< CH4SWEN (Bit 4)                                       */
#define PWM_CHOSWCR_CH4SWEN_Msk           (0x10UL)                  /*!< CH4SWEN (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CH5SWEN_Pos           (5UL)                     /*!< CH5SWEN (Bit 5)                                       */
#define PWM_CHOSWCR_CH5SWEN_Msk           (0x20UL)                  /*!< CH5SWEN (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CH6SWEN_Pos           (6UL)                     /*!< CH6SWEN (Bit 6)                                       */
#define PWM_CHOSWCR_CH6SWEN_Msk           (0x40UL)                  /*!< CH6SWEN (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CH7SWEN_Pos           (7UL)                     /*!< CH7SWEN (Bit 7)                                       */
#define PWM_CHOSWCR_CH7SWEN_Msk           (0x80UL)                  /*!< CH7SWEN (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CHSWEN_Msk            (0xffUL)                  /*!< CHSWEN  (Bitfield-Mask: 0xff)                         */
#define PWM_CHOSWCR_CH0SWCV_Pos           (8UL)                     /*!< CH0SWCV (Bit 8)                                       */
#define PWM_CHOSWCR_CH0SWCV_Msk           (0x100UL)                 /*!< CH0SWCV (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CH1SWCV_Pos           (9UL)                     /*!< CH1SWCV (Bit 9)                                       */
#define PWM_CHOSWCR_CH1SWCV_Msk           (0x200UL)                 /*!< CH1SWCV (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CH2SWCV_Pos           (10UL)                    /*!< CH2SWCV (Bit 10)                                      */
#define PWM_CHOSWCR_CH2SWCV_Msk           (0x400UL)                 /*!< CH2SWCV (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CH3SWCV_Pos           (11UL)                    /*!< CH3SWCV (Bit 11)                                      */
#define PWM_CHOSWCR_CH3SWCV_Msk           (0x800UL)                 /*!< CH3SWCV (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CH4SWCV_Pos           (12UL)                    /*!< CH4SWCV (Bit 12)                                      */
#define PWM_CHOSWCR_CH4SWCV_Msk           (0x1000UL)                /*!< CH4SWCV (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CH5SWCV_Pos           (13UL)                    /*!< CH5SWCV (Bit 13)                                      */
#define PWM_CHOSWCR_CH5SWCV_Msk           (0x2000UL)                /*!< CH5SWCV (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CH6SWCV_Pos           (14UL)                    /*!< CH6SWCV (Bit 14)                                      */
#define PWM_CHOSWCR_CH6SWCV_Msk           (0x4000UL)                /*!< CH6SWCV (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CH7SWCV_Pos           (15UL)                    /*!< CH7SWCV (Bit 15)                                      */
#define PWM_CHOSWCR_CH7SWCV_Msk           (0x8000UL)                /*!< CH7SWCV (Bitfield-Mask: 0x01)                         */
#define PWM_CHOSWCR_CHSWCV_Msk            (0xff00UL)                /*!< CHSWCV  (Bitfield-Mask: 0xff00)                       */

/* =========================================================================================================================== */
/* ================                                           PWDT                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  INIT0  ========================================================= */
#define PWDT_INIT0_OVF_Pos                (0UL)                     /*!< OVF (Bit 0)                                           */
#define PWDT_INIT0_OVF_Msk                (0x1UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
#define PWDT_INIT0_RDYF_Pos               (1UL)                     /*!< RDYF (Bit 1)                                          */
#define PWDT_INIT0_RDYF_Msk               (0x2UL)                   /*!< RDYF (Bitfield-Mask: 0x01)                            */
#define PWDT_INIT0_OVIE_Pos               (3UL)                     /*!< OVIE (Bit 3)                                          */
#define PWDT_INIT0_OVIE_Msk               (0x8UL)                   /*!< OVIE (Bitfield-Mask: 0x01)                            */
#define PWDT_INIT0_PRDYIE_Pos             (4UL)                     /*!< PRDYIE (Bit 4)                                        */
#define PWDT_INIT0_PRDYIE_Msk             (0x10UL)                  /*!< PRDYIE (Bitfield-Mask: 0x01)                          */
#define PWDT_INIT0_IE_Pos                 (5UL)                     /*!< IE (Bit 5)                                            */
#define PWDT_INIT0_IE_Msk                 (0x20UL)                  /*!< IE (Bitfield-Mask: 0x01)                              */
#define PWDT_INIT0_PWDTEN_Pos             (6UL)                     /*!< PWDTEN (Bit 6)                                        */
#define PWDT_INIT0_PWDTEN_Msk             (0x40UL)                  /*!< PWDTEN (Bitfield-Mask: 0x01)                          */
#define PWDT_INIT0_PSC0_Pos               (7UL)                     /*!< PSC0 (Bit 7)                                          */
#define PWDT_INIT0_PSC0_Msk               (0x380UL)                 /*!< PSC0 (Bitfield-Mask: 0x07)                            */
#define PWDT_INIT0_EDGE_Pos               (10UL)                    /*!< EDGE (Bit 10)                                         */
#define PWDT_INIT0_EDGE_Msk               (0xc00UL)                 /*!< EDGE (Bitfield-Mask: 0x03)                            */
#define PWDT_INIT0_PINSEL_Pos             (12UL)                    /*!< PINSEL (Bit 12)                                       */
#define PWDT_INIT0_PINSEL_Msk             (0x3000UL)                /*!< PINSEL (Bitfield-Mask: 0x03)                          */
#define PWDT_INIT0_PSC1_Pos               (14UL)                    /*!< PSC1 (Bit 14)                                         */
#define PWDT_INIT0_PSC1_Msk               (0xc000UL)                /*!< PSC1 (Bitfield-Mask: 0x03)                            */
#define PWDT_INIT0_PPW_Pos                (16UL)                    /*!< PPW (Bit 16)                                          */
#define PWDT_INIT0_PPW_Msk                (0xffff0000UL)            /*!< PPW (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  NPW  ========================================================== */
#define PWDT_NPW_NPW_Pos                  (0UL)                     /*!< NPW (Bit 0)                                           */
#define PWDT_NPW_NPW_Msk                  (0xffffUL)                /*!< NPW (Bitfield-Mask: 0xffff)                           */
#define PWDT_NPW_PWDTC_Pos                (16UL)                    /*!< PWDTC (Bit 16)                                        */
#define PWDT_NPW_PWDTC_Msk                (0xffff0000UL)            /*!< PWDTC (Bitfield-Mask: 0xffff)                         */
/* =========================================================  INIT1  ========================================================= */
#define PWDT_INIT1_FILTVAL_Pos            (0UL)                     /*!< FILTVAL (Bit 0)                                       */
#define PWDT_INIT1_FILTVAL_Msk            (0xfUL)                   /*!< FILTVAL (Bitfield-Mask: 0x0f)                         */
#define PWDT_INIT1_FILTPSC_Pos            (4UL)                     /*!< FILTPSC (Bit 4)                                       */
#define PWDT_INIT1_FILTPSC_Msk            (0xf0UL)                  /*!< FILTPSC (Bitfield-Mask: 0x0f)                         */
#define PWDT_INIT1_FILTEN_Pos             (8UL)                     /*!< FILTEN (Bit 8)                                        */
#define PWDT_INIT1_FILTEN_Msk             (0x100UL)                 /*!< FILTEN (Bitfield-Mask: 0x01)                          */
#define PWDT_INIT1_HALLEN_Pos             (9UL)                     /*!< HALLEN (Bit 9)                                        */
#define PWDT_INIT1_HALLEN_Msk             (0x200UL)                 /*!< HALLEN (Bitfield-Mask: 0x01)                          */
#define PWDT_INIT1_TIMEN_Pos              (10UL)                    /*!< TIMEN (Bit 10)                                        */
#define PWDT_INIT1_TIMEN_Msk              (0x400UL)                 /*!< TIMEN (Bitfield-Mask: 0x01)                           */
#define PWDT_INIT1_CMPEN_Pos              (11UL)                    /*!< CMPEN (Bit 11)                                        */
#define PWDT_INIT1_CMPEN_Msk              (0x800UL)                 /*!< CMPEN (Bitfield-Mask: 0x01)                           */
#define PWDT_INIT1_TIMLDVAL_Pos           (12UL)                    /*!< TIMLDVAL (Bit 12)                                     */
#define PWDT_INIT1_TIMLDVAL_Msk           (0xffff000UL)             /*!< TIMLDVAL (Bitfield-Mask: 0xffff)                      */
#define PWDT_INIT1_HALLSTATUS_Pos         (28UL)                    /*!< HALLSTATUS (Bit 28)                                   */
#define PWDT_INIT1_HALLSTATUS_Msk         (0x70000000UL)            /*!< HALLSTATUS (Bitfield-Mask: 0x07)                      */


/* =========================================================================================================================== */
/* ================                                        TIMER_CTRL                                         ================ */
/* =========================================================================================================================== */

/* ==========================================================  MCR  ========================================================== */
#define TIMER_CTRL_MCR_MDIS_Pos           (1UL)                     /*!< MDIS (Bit 1)                                          */
#define TIMER_CTRL_MCR_MDIS_Msk           (0x2UL)                   /*!< MDIS (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                      TIMER_CHANNEL                                        ================ */
/* =========================================================================================================================== */

/* =========================================================  LDVAL  ========================================================= */
#define TIMER_CHANNEL_LDVAL_LDVAL_Pos     (0UL)                     /*!< LDVAL (Bit 0)                                         */
#define TIMER_CHANNEL_LDVAL_LDVAL_Msk     (0xffffffffUL)            /*!< LDVAL (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  CVAL  ========================================================== */
#define TIMER_CHANNEL_CVAL_CVAL_Pos       (0UL)                     /*!< CVAL (Bit 0)                                          */
#define TIMER_CHANNEL_CVAL_CVAL_Msk       (0xffffffffUL)            /*!< CVAL (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  INIT  ========================================================== */
#define TIMER_CHANNEL_INIT_TEN_Pos        (0UL)                     /*!< TEN (Bit 0)                                           */
#define TIMER_CHANNEL_INIT_TEN_Msk        (0x1UL)                   /*!< TEN (Bitfield-Mask: 0x01)                             */
#define TIMER_CHANNEL_INIT_TIE_Pos        (1UL)                     /*!< TIE (Bit 1)                                           */
#define TIMER_CHANNEL_INIT_TIE_Msk        (0x2UL)                   /*!< TIE (Bitfield-Mask: 0x01)                             */
#define TIMER_CHANNEL_INIT_LINKEN_Pos     (2UL)                     /*!< LINKEN (Bit 2)                                        */
#define TIMER_CHANNEL_INIT_LINKEN_Msk     (0x4UL)                   /*!< LINKEN (Bitfield-Mask: 0x01)                          */
/* ==========================================================  TF  =========================================================== */
#define TIMER_CHANNEL_TF_TFLG_Pos         (0UL)                     /*!< TFLG (Bit 0)                                          */
#define TIMER_CHANNEL_TF_TFLG_Msk         (0x1UL)                   /*!< TFLG (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                            CTU                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  CONFIG0  ======================================================== */
#define CTU_CONFIG0_RXDFE_Pos             (9UL)                     /*!< RXDFE (Bit 9)                                         */
#define CTU_CONFIG0_RXDFE_Msk             (0x200UL)                 /*!< RXDFE (Bitfield-Mask: 0x01)                           */
#define CTU_CONFIG0_RTCC_Pos              (10UL)                    /*!< RTCC (Bit 10)                                         */
#define CTU_CONFIG0_RTCC_Msk              (0x400UL)                 /*!< RTCC (Bitfield-Mask: 0x01)                            */
#define CTU_CONFIG0_ACIC_Pos              (11UL)                    /*!< ACIC (Bit 11)                                         */
#define CTU_CONFIG0_ACIC_Msk              (0x800UL)                 /*!< ACIC (Bitfield-Mask: 0x01)                            */
#define CTU_CONFIG0_RXDCE_Pos             (12UL)                    /*!< RXDCE (Bit 12)                                        */
#define CTU_CONFIG0_RXDCE_Msk             (0x1000UL)                /*!< RXDCE (Bitfield-Mask: 0x01)                           */
#define CTU_CONFIG0_PWMSYNC_Pos           (14UL)                    /*!< PWMSYNC (Bit 14)                                      */
#define CTU_CONFIG0_PWMSYNC_Msk           (0x4000UL)                /*!< PWMSYNC (Bitfield-Mask: 0x01)                         */
#define CTU_CONFIG0_TXDME_Pos             (15UL)                    /*!< TXDME (Bit 15)                                        */
#define CTU_CONFIG0_TXDME_Msk             (0x8000UL)                /*!< TXDME (Bitfield-Mask: 0x01)                           */
#define CTU_CONFIG0_PSC_Pos               (16UL)                    /*!< PSC (Bit 16)                                          */
#define CTU_CONFIG0_PSC_Msk               (0x70000UL)               /*!< PSC (Bitfield-Mask: 0x07)                             */
#define CTU_CONFIG0_ADHWT0_Pos            (20UL)                    /*!< ADHWT0 (Bit 20)                                       */
#define CTU_CONFIG0_ADHWT0_Msk            (0x700000UL)              /*!< ADHWT0 (Bitfield-Mask: 0x07)                          */
#define CTU_CONFIG0_DLYACT0_Pos           (23UL)                    /*!< DLYACT0 (Bit 23)                                      */
#define CTU_CONFIG0_DLYACT0_Msk           (0x800000UL)              /*!< DLYACT0 (Bitfield-Mask: 0x01)                         */
#define CTU_CONFIG0_DELAY0_Pos            (24UL)                    /*!< DELAY0 (Bit 24)                                       */
#define CTU_CONFIG0_DELAY0_Msk            (0xff000000UL)            /*!< DELAY0 (Bitfield-Mask: 0xff)                          */
/* ========================================================  CONFIG1  ======================================================== */
#define CTU_CONFIG1_ADHWT1_Pos            (6UL)                     /*!< ADHWT1 (Bit 6)                                        */
#define CTU_CONFIG1_ADHWT1_Msk            (0x1c0UL)                 /*!< ADHWT1 (Bitfield-Mask: 0x07)                          */
#define CTU_CONFIG1_PWDT0IN3S_Pos         (9UL)                     /*!< PWDT0IN3S (Bit 9)                                     */
#define CTU_CONFIG1_PWDT0IN3S_Msk         (0x600UL)                 /*!< PWDT0IN3S (Bitfield-Mask: 0x03)                       */
#define CTU_CONFIG1_PWDT1IN3S_Pos         (11UL)                    /*!< PWDT1IN3S (Bit 11)                                    */
#define CTU_CONFIG1_PWDT1IN3S_Msk         (0x1800UL)                /*!< PWDT1IN3S (Bitfield-Mask: 0x03)                       */
#define CTU_CONFIG1_DLYACT1_Pos           (22UL)                    /*!< DLYACT1 (Bit 22)                                      */
#define CTU_CONFIG1_DLYACT1_Msk           (0x400000UL)              /*!< DLYACT1 (Bitfield-Mask: 0x01)                         */
#define CTU_CONFIG1_DELAY1_Pos            (23UL)                    /*!< DELAY1 (Bit 23)                                       */
#define CTU_CONFIG1_DELAY1_Msk            (0x7f800000UL)            /*!< DELAY1 (Bitfield-Mask: 0xff)                          */


/* =========================================================================================================================== */
/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */

/* ========================================================  TOP_RST  ======================================================== */
#define DMA_TOP_RST_WARM_RST_Pos          (0UL)                     /*!< WARM_RST (Bit 0)                                      */
#define DMA_TOP_RST_WARM_RST_Msk          (0x1UL)                   /*!< WARM_RST (Bitfield-Mask: 0x01)                        */
#define DMA_TOP_RST_HARD_RST_Pos          (1UL)                     /*!< HARD_RST (Bit 1)                                      */
#define DMA_TOP_RST_HARD_RST_Msk          (0x2UL)                   /*!< HARD_RST (Bitfield-Mask: 0x01)                        */


/* =========================================================================================================================== */
/* ================                                       DMA_Channel                                         ================ */
/* =========================================================================================================================== */

/* ========================================================  STATUS  ========================================================= */
#define DMA_CHANNEL_STATUS_FINISH_Pos   (0UL)                       /*!< FINISH (Bit 0)                                        */
#define DMA_CHANNEL_STATUS_FINISH_Msk   (0x1UL)                     /*!< FINISH (Bitfield-Mask: 0x01)                          */
#define DMA_CHANNEL_STATUS_HALF_FINISH_Pos (1UL)                    /*!< HALF_FINISH (Bit 1)                                   */
#define DMA_CHANNEL_STATUS_HALF_FINISH_Msk (0x2UL)                  /*!< HALF_FINISH (Bitfield-Mask: 0x01)                     */
#define DMA_CHANNEL_STATUS_TRANS_ERROR_Pos (2UL)                    /*!< TRANS_ERROR (Bit 2)                                   */
#define DMA_CHANNEL_STATUS_TRANS_ERROR_Msk (0x4UL)                  /*!< TRANS_ERROR (Bitfield-Mask: 0x01)                     */
/* ========================================================  INTEN  ========================================================== */
#define DMA_CHANNEL_INTEN_FINISH_INTERRUPT_ENABLE_Pos (0UL)         /*!< FINISH_INTERRUPT_ENABLE (Bit 0)                       */
#define DMA_CHANNEL_INTEN_FINISH_INTERRUPT_ENABLE_Msk (0x1UL)       /*!< FINISH_INTERRUPT_ENABLE (Bitfield-Mask: 0x01)         */
#define DMA_CHANNEL_INTEN_HALF_FINISH_INTERRUPT_ENABLE_Pos (1UL)    /*!< HALF_FINISH_INTERRUPT_ENABLE (Bit 1)                  */
#define DMA_CHANNEL_INTEN_HALF_FINISH_INTERRUPT_ENABLE_Msk (0x2UL)  /*!< HALF_FINISH_INTERRUPT_ENABLE (Bitfield-Mask: 0x01)   */
#define DMA_CHANNEL_INTEN_TRANS_ERROR_INTERRUPT_ENABLE_Pos (2UL)    /*!< TRANS_ERROR_INTERRUPT_ENABLE (Bit 2)                  */
#define DMA_CHANNEL_INTEN_TRANS_ERROR_INTERRUPT_ENABLE_Msk (0x4UL)  /*!< TRANS_ERROR_INTERRUPT_ENABLE (Bitfield-Mask: 0x01)   */
/* =========================================================  RST  =========================================================== */
#define DMA_CHANNEL_RST_WARM_RST_Pos    (0UL)                       /*!< WARM_RST (Bit 0)                                      */
#define DMA_CHANNEL_RST_WARM_RST_Msk    (0x1UL)                     /*!< WARM_RST (Bitfield-Mask: 0x01)                        */
#define DMA_CHANNEL_RST_HARD_RST_Pos    (1UL)                       /*!< HARD_RST (Bit 1)                                      */
#define DMA_CHANNEL_RST_HARD_RST_Msk    (0x2UL)                     /*!< HARD_RST (Bitfield-Mask: 0x01)                        */
#define DMA_CHANNEL_RST_FLUSH_Pos       (2UL)                       /*!< FLUSH (Bit 2)                                         */
#define DMA_CHANNEL_RST_FLUSH_Msk       (0x4UL)                     /*!< FLUSH (Bitfield-Mask: 0x01)                           */
/* ========================================================  STOP  =========================================================== */
#define DMA_CHANNEL_STOP_STOP_Pos       (0UL)                       /*!< STOP (Bit 0)                                          */
#define DMA_CHANNEL_STOP_STOP_Msk       (0x1UL)                     /*!< STOP (Bitfield-Mask: 0x01)                            */
/* =======================================================  CONFIG  ========================================================== */
#define DMA_CHANNEL_CONFIG_MEM2MEM_Pos  (0UL)                       /*!< MEM2MEM (Bit 0)                                       */
#define DMA_CHANNEL_CONFIG_MEM2MEM_Msk  (0x1UL)                     /*!< MEM2MEM (Bitfield-Mask: 0x01)                         */
#define DMA_CHANNEL_CONFIG_CHAN_PRIORITY_Pos (1UL)                  /*!< CHAN_PRIORITY (Bit 1)                                 */
#define DMA_CHANNEL_CONFIG_CHAN_PRIORITY_Msk (0x6UL)                /*!< CHAN_PRIORITY (Bitfield-Mask: 0x03)                   */
#define DMA_CHANNEL_CONFIG_MEM_SIZE_Pos (3UL)                       /*!< MEM_SIZE (Bit 3)                                      */
#define DMA_CHANNEL_CONFIG_MEM_SIZE_Msk (0x18UL)                    /*!< MEM_SIZE (Bitfield-Mask: 0x03)                        */
#define DMA_CHANNEL_CONFIG_PERIPH_SIZE_Pos (5UL)                    /*!< PERIPH_SIZE (Bit 5)                                   */
#define DMA_CHANNEL_CONFIG_PERIPH_SIZE_Msk (0x60UL)                 /*!< PERIPH_SIZE (Bitfield-Mask: 0x03)                     */
#define DMA_CHANNEL_CONFIG_MEM_INCREMENT_Pos (7UL)                  /*!< MEM_INCREMENT (Bit 7)                                 */
#define DMA_CHANNEL_CONFIG_MEM_INCREMENT_Msk (0x80UL)               /*!< MEM_INCREMENT (Bitfield-Mask: 0x01)                   */
#define DMA_CHANNEL_CONFIG_PERIPH_INCREMENT_Pos (8UL)               /*!< PERIPH_INCREMENT (Bit 8)                              */
#define DMA_CHANNEL_CONFIG_PERIPH_INCREMENT_Msk (0x100UL)           /*!< PERIPH_INCREMENT (Bitfield-Mask: 0x01)                */
#define DMA_CHANNEL_CONFIG_CHAN_CIRCULAR_Pos (9UL)                  /*!< CHAN_CIRCULAR (Bit 9)                                 */
#define DMA_CHANNEL_CONFIG_CHAN_CIRCULAR_Msk (0x200UL)              /*!< CHAN_CIRCULAR (Bitfield-Mask: 0x01)                   */
#define DMA_CHANNEL_CONFIG_CHAN_DIR_Pos (10UL)                      /*!< CHAN_DIR (Bit 10)                                     */
#define DMA_CHANNEL_CONFIG_CHAN_DIR_Msk (0x400UL)                   /*!< CHAN_DIR (Bitfield-Mask: 0x01)                        */
#define DMA_CHANNEL_CONFIG_MEM_BYTE_MODE_Pos (11UL)                 /*!< MEM_BYTE_MODE (Bit 11)                                */
#define DMA_CHANNEL_CONFIG_MEM_BYTE_MODE_Msk (0x1800UL)             /*!< MEM_BYTE_MODE (Bitfield-Mask: 0x03)                   */
#define DMA_CHANNEL_CONFIG_PERIPH_SEL_Pos (16UL)                    /*!< PERIPH_SEL (Bit 16)                                   */
#define DMA_CHANNEL_CONFIG_PERIPH_SEL_Msk (0xf0000UL)               /*!< PERIPH_SEL (Bitfield-Mask: 0x0f)                      */
/* =====================================================  CHAN_LENGTH  ======================================================= */
#define DMA_CHANNEL_CHAN_LENGTH_CHAN_LENGTH_Pos (0UL)               /*!< CHAN_LENGTH (Bit 0)                                   */
#define DMA_CHANNEL_CHAN_LENGTH_CHAN_LENGTH_Msk (0xffffUL)          /*!< CHAN_LENGTH (Bitfield-Mask: 0xffff)                   */
/* ===================================================  MEM_START_ADDR  ====================================================== */
#define DMA_CHANNEL_MEM_START_ADDR_MEM_START_ADDR_Pos (0UL)         /*!< MEM_START_ADDR (Bit 0)                                */
#define DMA_CHANNEL_MEM_START_ADDR_MEM_START_ADDR_Msk (0xffffffffUL)   /*!< MEM_START_ADDR (Bitfield-Mask: 0xffffffff)         */
/* ====================================================  MEM_END_ADDR  ======================================================= */
#define DMA_CHANNEL_MEM_END_ADDR_MEM_END_ADDR_Pos (0UL)             /*!< MEM_END_ADDR (Bit 0)                                  */
#define DMA_CHANNEL_MEM_END_ADDR_MEM_END_ADDR_Msk (0xffffffffUL)    /*!< MEM_END_ADDR (Bitfield-Mask: 0xffffffff)              */
/* =====================================================  PERIPH_ADDR  ======================================================= */
#define DMA_CHANNEL_PERIPH_ADDR_PERIPH_ADDR_Pos (0UL)               /*!< PERIPH_ADDR (Bit 0)                                   */
#define DMA_CHANNEL_PERIPH_ADDR_PERIPH_ADDR_Msk (0xffffffffUL)      /*!< PERIPH_ADDR (Bitfield-Mask: 0xffffffff)               */
/* =====================================================  CHAN_ENABLE  ======================================================= */
#define DMA_CHANNEL_CHAN_ENABLE_CHAN_ENABLE_Pos (0UL)               /*!< CHAN_ENABLE (Bit 0)                                   */
#define DMA_CHANNEL_CHAN_ENABLE_CHAN_ENABLE_Msk (0x1UL)             /*!< CHAN_ENABLE (Bitfield-Mask: 0x01)                     */
/* ===================================================  DATA_TRANS_NUM  ====================================================== */
#define DMA_CHANNEL_DATA_TRANS_NUM_DATA_TRANS_NUM_Pos (0UL)         /*!< DATA_TRANS_NUM (Bit 0)                                */
#define DMA_CHANNEL_DATA_TRANS_NUM_DATA_TRANS_NUM_Msk (0xffffUL)    /*!< DATA_TRANS_NUM (Bitfield-Mask: 0xffff)                */
/* ====================================================  FIFO_LEFT_NUM  ====================================================== */
#define DMA_CHANNEL_FIFO_LEFT_NUM_FIFO_LEFT_NUM_Pos (0UL)           /*!< FIFO_LEFT_NUM (Bit 0)                                 */
#define DMA_CHANNEL_FIFO_LEFT_NUM_FIFO_LEFT_NUM_Msk (0x3fUL)        /*!< FIFO_LEFT_NUM (Bitfield-Mask: 0x3f)                   */


/* =========================================================================================================================== */
/* ================                                            WDG                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CS0  ========================================================== */
#define WDG_CS0_UPDATE_Pos                (5UL)                     /*!< UPDATE (Bit 5)                                        */
#define WDG_CS0_UPDATE_Msk                (0x20UL)                  /*!< UPDATE (Bitfield-Mask: 0x01)                          */
#define WDG_CS0_INT_Pos                   (6UL)                     /*!< INT (Bit 6)                                           */
#define WDG_CS0_INT_Msk                   (0x40UL)                  /*!< INT (Bitfield-Mask: 0x01)                             */
#define WDG_CS0_EN_Pos                    (7UL)                     /*!< EN (Bit 7)                                            */
#define WDG_CS0_EN_Msk                    (0x80UL)                  /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CS1  ========================================================== */
#define WDG_CS1_CLK_Pos                   (0UL)                     /*!< CLK (Bit 0)                                           */
#define WDG_CS1_CLK_Msk                   (0x3UL)                   /*!< CLK (Bitfield-Mask: 0x03)                             */
#define WDG_CS1_PRES_Pos                  (4UL)                     /*!< PRES (Bit 4)                                          */
#define WDG_CS1_PRES_Msk                  (0x10UL)                  /*!< PRES (Bitfield-Mask: 0x01)                            */
#define WDG_CS1_FLG_Pos                   (6UL)                     /*!< FLG (Bit 6)                                           */
#define WDG_CS1_FLG_Msk                   (0x40UL)                  /*!< FLG (Bitfield-Mask: 0x01)                             */
#define WDG_CS1_WIN_Pos                   (7UL)                     /*!< WIN (Bit 7)                                           */
#define WDG_CS1_WIN_Msk                   (0x80UL)                  /*!< WIN (Bitfield-Mask: 0x01)                             */
/* ==========================================================  CNT  ========================================================== */
#define WDG_CNT_CNT_Pos                   (0UL)                     /*!< CNT (Bit 0)                                           */
#define WDG_CNT_CNT_Msk                   (0xffffffffUL)            /*!< CNT (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  TOVAL  ========================================================= */
#define WDG_TOVAL_TOVAL_Pos               (0UL)                     /*!< TOVAL (Bit 0)                                         */
#define WDG_TOVAL_TOVAL_Msk               (0xffffffffUL)            /*!< TOVAL (Bitfield-Mask: 0xffffffff)                     */
/* ==========================================================  WIN  ========================================================== */
#define WDG_WIN_WIN_Pos                   (0UL)                     /*!< WIN (Bit 0)                                           */
#define WDG_WIN_WIN_Msk                   (0xffffffffUL)            /*!< WIN (Bitfield-Mask: 0xffffffff)                       */


/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  SC  =========================================================== */
#define RTC_SC_RTCO_Pos                   (4UL)                     /*!< RTCO (Bit 4)                                          */
#define RTC_SC_RTCO_Msk                   (0x10UL)                  /*!< RTCO (Bitfield-Mask: 0x01)                            */
#define RTC_SC_RTIE_Pos                   (6UL)                     /*!< RTIE (Bit 6)                                          */
#define RTC_SC_RTIE_Msk                   (0x40UL)                  /*!< RTIE (Bitfield-Mask: 0x01)                            */
#define RTC_SC_RTIF_Pos                   (7UL)                     /*!< RTIF (Bit 7)                                          */
#define RTC_SC_RTIF_Msk                   (0x80UL)                  /*!< RTIF (Bitfield-Mask: 0x01)                            */
#define RTC_SC_RTCLKS_Pos                 (14UL)                    /*!< RTCLKS (Bit 14)                                       */
#define RTC_SC_RTCLKS_Msk                 (0xc000UL)                /*!< RTCLKS (Bitfield-Mask: 0x03)                          */
#define RTC_SC_RPIE_Pos                   (16UL)                    /*!< RPIE (Bit 16)                                         */
#define RTC_SC_RPIE_Msk                   (0x10000UL)               /*!< RPIE (Bitfield-Mask: 0x01)                            */
#define RTC_SC_RPIF_Pos                   (17UL)                    /*!< RPIF (Bit 17)                                         */
#define RTC_SC_RPIF_Msk                   (0x20000UL)               /*!< RPIF (Bitfield-Mask: 0x01)                            */
/* ==========================================================  MOD  ========================================================== */
#define RTC_MOD_MOD_Pos                   (0UL)                     /*!< MOD (Bit 0)                                           */
#define RTC_MOD_MOD_Msk                   (0xffffffffUL)            /*!< MOD (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  CNT  ========================================================== */
#define RTC_CNT_CNT_Pos                   (0UL)                     /*!< CNT (Bit 0)                                           */
#define RTC_CNT_CNT_Msk                   (0xffffffffUL)            /*!< CNT (Bitfield-Mask: 0xffffffff)                       */
/* ==========================================================  PS  =========================================================== */
#define RTC_PS_RTCPS_Pos                  (0UL)                     /*!< RTCPS (Bit 0)                                         */
#define RTC_PS_RTCPS_Msk                  (0xfffffUL)               /*!< RTCPS (Bitfield-Mask: 0xfffff)                        */
/* =========================================================  PSCNT  ========================================================= */
#define RTC_PSCNT_PSCNT_Pos               (0UL)                     /*!< PSCNT (Bit 0)                                         */
#define RTC_PSCNT_PSCNT_Msk               (0xfffffUL)               /*!< PSCNT (Bitfield-Mask: 0xfffff)                        */


/* =========================================================================================================================== */
/* ================                                         MMDIVSQRT                                         ================ */
/* =========================================================================================================================== */

/* =========================================================  DEND  ========================================================== */
#define MMDIVSQRT_DEND_DEND_Pos            (0UL)                     /*!< DEND (Bit 0)                                          */
#define MMDIVSQRT_DEND_DEND_Msk            (0xffffffffUL)            /*!< DEND (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  DSOR  ========================================================== */
#define MMDIVSQRT_DSOR_DSOR_Pos            (0UL)                     /*!< DSOR (Bit 0)                                          */
#define MMDIVSQRT_DSOR_DSOR_Msk            (0xffffffffUL)            /*!< DSOR (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  DSFT  ========================================================== */
#define MMDIVSQRT_DSFT_DSFT_Pos            (0UL)                     /*!< DSFT (Bit 0)                                          */
#define MMDIVSQRT_DSFT_DSFT_Msk            (0x1fUL)                  /*!< DSFT (Bitfield-Mask: 0x1f)                            */
/* =========================================================  RCNDX  ========================================================= */
#define MMDIVSQRT_RCNDX_RCNDX_Pos          (0UL)                     /*!< RCNDX (Bit 0)                                         */
#define MMDIVSQRT_RCNDX_RCNDX_Msk          (0xffffffffUL)            /*!< RCNDX (Bitfield-Mask: 0xffffffff)                     */
/* =========================================================  RCNDY  ========================================================= */
#define MMDIVSQRT_RCNDY_RCNDY_Pos          (0UL)                     /*!< RCNDY (Bit 0)                                         */
#define MMDIVSQRT_RCNDY_RCNDY_Msk          (0xffffffffUL)            /*!< RCNDY (Bitfield-Mask: 0xffffffff)                     */
/* ==========================================================  CSR  ========================================================== */
#define MMDIVSQRT_CSR_USIGN_Pos            (1UL)                     /*!< USIGN (Bit 1)                                         */
#define MMDIVSQRT_CSR_USIGN_Msk            (0x2UL)                   /*!< USIGN (Bitfield-Mask: 0x01)                           */
#define MMDIVSQRT_CSR_REM_Pos              (2UL)                     /*!< REM (Bit 2)                                           */
#define MMDIVSQRT_CSR_REM_Msk              (0x4UL)                   /*!< REM (Bitfield-Mask: 0x01)                             */
#define MMDIVSQRT_CSR_SQRT_Pos             (29UL)                    /*!< SQRT (Bit 29)                                         */
#define MMDIVSQRT_CSR_SQRT_Msk             (0x20000000UL)            /*!< SQRT (Bitfield-Mask: 0x01)                            */
#define MMDIVSQRT_CSR_DIV_Pos              (30UL)                    /*!< DIV (Bit 30)                                          */
#define MMDIVSQRT_CSR_DIV_Msk              (0x40000000UL)            /*!< DIV (Bitfield-Mask: 0x01)                             */
#define MMDIVSQRT_CSR_BUSY_Pos            (31UL)                    /*!< BUSY (Bit 31)                                         */
#define MMDIVSQRT_CSR_BUSY_Msk            (0x80000000UL)            /*!< BUSY (Bitfield-Mask: 0x01)                            */
/* ========================================================  RESULT  ========================================================= */
#define MMDIVSQRT_RESULT_RESULT_Pos        (0UL)                     /*!< RESULT (Bit 0)                                        */
#define MMDIVSQRT_RESULT_RESULT_Msk        (0xffffffffUL)            /*!< RESULT (Bitfield-Mask: 0xffffffff)                    */


/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  DATA  ========================================================== */
#define CRC_DATA_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
#define CRC_DATA_DATA_Msk                 (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  POLY  ========================================================== */
#define CRC_POLY_POLY_Pos                 (0UL)                     /*!< POLY (Bit 0)                                          */
#define CRC_POLY_POLY_Msk                 (0xffffffffUL)            /*!< POLY (Bitfield-Mask: 0xffffffff)                      */
/* =========================================================  CTRL  ========================================================== */
#define CRC_CTRL_TCRC_Pos                 (0UL)                     /*!< TCRC (Bit 0)                                          */
#define CRC_CTRL_TCRC_Msk                 (0x1UL)                   /*!< TCRC (Bitfield-Mask: 0x01)                            */
#define CRC_CTRL_WAS_Pos                  (1UL)                     /*!< WAS (Bit 1)                                           */
#define CRC_CTRL_WAS_Msk                  (0x2UL)                   /*!< WAS (Bitfield-Mask: 0x01)                             */
#define CRC_CTRL_FXOR_Pos                 (2UL)                     /*!< FXOR (Bit 2)                                          */
#define CRC_CTRL_FXOR_Msk                 (0x4UL)                   /*!< FXOR (Bitfield-Mask: 0x01)                            */
#define CRC_CTRL_TOTR_Pos                 (4UL)                     /*!< TOTR (Bit 4)                                          */
#define CRC_CTRL_TOTR_Msk                 (0x30UL)                  /*!< TOTR (Bitfield-Mask: 0x03)                            */
#define CRC_CTRL_TOTW_Pos                 (6UL)                     /*!< TOTW (Bit 6)                                          */
#define CRC_CTRL_TOTW_Msk                 (0xc0UL)                  /*!< TOTW (Bitfield-Mask: 0x03)                            */


/* =========================================================================================================================== */
/* ================                                         ECC_SRAM                                          ================ */
/* =========================================================================================================================== */

/* =========================================================  CTRL  ========================================================== */
#define ECC_SRAM_CTRL_ERR2_IRQEN_Pos      (1UL)                     /*!< ERR2_IRQEN (Bit 1)                                    */
#define ECC_SRAM_CTRL_ERR2_IRQEN_Msk      (0x2UL)                   /*!< ERR2_IRQEN (Bitfield-Mask: 0x01)                      */
#define ECC_SRAM_CTRL_ERR2_STATUS_Pos     (2UL)                     /*!< ERR2_STATUS (Bit 2)                                   */
#define ECC_SRAM_CTRL_ERR2_STATUS_Msk     (0x4UL)                   /*!< ERR2_STATUS (Bitfield-Mask: 0x01)                     */
#define ECC_SRAM_CTRL_ERR_STATUS_Pos      (4UL)                     /*!< ERR_STATUS (Bit 4)                                    */
#define ECC_SRAM_CTRL_ERR_STATUS_Msk      (0x30UL)                  /*!< ERR_STATUS (Bitfield-Mask: 0x03)                      */
/* =======================================================  ERR1_ADDR  ======================================================= */
#define ECC_SRAM_ERR1_ADDR_ERR1_ADDR_Pos  (0UL)                     /*!< ERR1_ADDR (Bit 0)                                     */
#define ECC_SRAM_ERR1_ADDR_ERR1_ADDR_Msk  (0x1fffUL)                /*!< ERR1_ADDR (Bitfield-Mask: 0x1fff)                     */
/* =======================================================  ERR2_ADDR  ======================================================= */
#define ECC_SRAM_ERR2_ADDR_ERR2_ADDR_Pos  (0UL)                     /*!< ERR2_ADDR (Bit 0)                                     */
#define ECC_SRAM_ERR2_ADDR_ERR2_ADDR_Msk  (0x1fffUL)                /*!< ERR2_ADDR (Bitfield-Mask: 0x1fff)                     */


/* =========================================================================================================================== */
/* ================                                          EFLASH                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  KEY  ========================================================== */
#define EFLASH_KEY_KEY_Pos                (0UL)                     /*!< KEY (Bit 0)                                           */
#define EFLASH_KEY_KEY_Msk                (0xffffffffUL)            /*!< KEY (Bitfield-Mask: 0xffffffff)                       */
/* =========================================================  INFO  ========================================================== */
#define EFLASH_INFO_RD_PRT_Pos            (0UL)                     /*!< RD_PRT (Bit 0)                                        */
#define EFLASH_INFO_RD_PRT_Msk            (0x1UL)                   /*!< RD_PRT (Bitfield-Mask: 0x01)                          */
#define EFLASH_INFO_WDG_EN_Pos            (1UL)                     /*!< WDG_EN (Bit 1)                                        */
#define EFLASH_INFO_WDG_EN_Msk            (0x2UL)                   /*!< WDG_EN (Bitfield-Mask: 0x01)                          */
#define EFLASH_INFO_LOCK_Pos              (31UL)                    /*!< LOCK (Bit 31)                                         */
#define EFLASH_INFO_LOCK_Msk              (0x80000000UL)            /*!< LOCK (Bitfield-Mask: 0x01)                            */
/* ========================================================  ADR_CMD  ======================================================== */
#define EFLASH_ADR_CMD_ADR_CMD_Pos        (0UL)                     /*!< ADR_CMD (Bit 0)                                       */
#define EFLASH_ADR_CMD_ADR_CMD_Msk        (0xffffffffUL)            /*!< ADR_CMD (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  CTRL0  ========================================================= */
#define EFLASH_CTRL0_CMD_CTL_Pos          (0UL)                     /*!< CMD_CTL (Bit 0)                                       */
#define EFLASH_CTRL0_CMD_CTL_Msk          (0xfUL)                   /*!< CMD_CTL (Bitfield-Mask: 0x0f)                         */
#define EFLASH_CTRL0_CMD_ST_Pos           (4UL)                     /*!< CMD_ST (Bit 4)                                        */
#define EFLASH_CTRL0_CMD_ST_Msk           (0x10UL)                  /*!< CMD_ST (Bitfield-Mask: 0x01)                          */
#define EFLASH_CTRL0_OPT_CMD_EN_Pos       (12UL)                    /*!< OPT_CMD_EN (Bit 12)                                   */
#define EFLASH_CTRL0_OPT_CMD_EN_Msk       (0x1000UL)                /*!< OPT_CMD_EN (Bitfield-Mask: 0x01)                      */
#define EFLASH_CTRL0_PROG_LENGTH_Pos      (16UL)                    /*!< PROG_LENGTH (Bit 16)                                  */
#define EFLASH_CTRL0_PROG_LENGTH_Msk      (0x3ff0000UL)             /*!< PROG_LENGTH (Bitfield-Mask: 0x3ff)                    */
#define EFLASH_CTRL0_HDFEN_Pos            (31UL)                    /*!< HDFEN (Bit 31)                                        */
#define EFLASH_CTRL0_HDFEN_Msk            (0x80000000UL)            /*!< HDFEN (Bitfield-Mask: 0x01)                           */
/* ==========================================================  SR0  ========================================================== */
#define EFLASH_SR0_CMD_BSY_Pos            (0UL)                     /*!< CMD_BSY (Bit 0)                                       */
#define EFLASH_SR0_CMD_BSY_Msk            (0x1UL)                   /*!< CMD_BSY (Bitfield-Mask: 0x01)                         */
#define EFLASH_SR0_EOP_Pos                (1UL)                     /*!< EOP (Bit 1)                                           */
#define EFLASH_SR0_EOP_Msk                (0x2UL)                   /*!< EOP (Bitfield-Mask: 0x01)                             */
#define EFLASH_SR0_WRER_Pos               (2UL)                     /*!< WRER (Bit 2)                                          */
#define EFLASH_SR0_WRER_Msk               (0x4UL)                   /*!< WRER (Bitfield-Mask: 0x01)                            */
#define EFLASH_SR0_RDER_Pos               (3UL)                     /*!< RDER (Bit 3)                                          */
#define EFLASH_SR0_RDER_Msk               (0x8UL)                   /*!< RDER (Bitfield-Mask: 0x01)                            */
#define EFLASH_SR0_PPERER_Pos             (4UL)                     /*!< PPERER (Bit 4)                                        */
#define EFLASH_SR0_PPERER_Msk             (0x10UL)                  /*!< PPERER (Bitfield-Mask: 0x01)                          */
#define EFLASH_SR0_PPADRER_Pos            (5UL)                     /*!< PPADRER (Bit 5)                                       */
#define EFLASH_SR0_PPADRER_Msk            (0x20UL)                  /*!< PPADRER (Bitfield-Mask: 0x01)                         */
#define EFLASH_SR0_ERAER_Pos              (6UL)                     /*!< ERAER (Bit 6)                                         */
#define EFLASH_SR0_ERAER_Msk              (0x40UL)                  /*!< ERAER (Bitfield-Mask: 0x01)                           */
#define EFLASH_SR0_VRER_Pos               (7UL)                     /*!< VRER (Bit 7)                                          */
#define EFLASH_SR0_VRER_Msk               (0x80UL)                  /*!< VRER (Bitfield-Mask: 0x01)                            */
#define EFLASH_SR0_OPTER_Pos              (8UL)                     /*!< OPTER (Bit 8)                                         */
#define EFLASH_SR0_OPTER_Msk              (0xf00UL)                 /*!< OPTER (Bitfield-Mask: 0x0f)                           */
#define EFLASH_SR0_FLUSH_Pos              (12UL)                    /*!< FLUSH (Bit 12)                                        */
#define EFLASH_SR0_FLUSH_Msk              (0x1000UL)                /*!< FLUSH (Bitfield-Mask: 0x01)                           */
/* =========================================================  CTRL1  ========================================================= */
#define EFLASH_CTRL1_CKDIV_Pos            (0UL)                     /*!< CKDIV (Bit 0)                                         */
#define EFLASH_CTRL1_CKDIV_Msk            (0x7fUL)                  /*!< CKDIV (Bitfield-Mask: 0x7f)                           */
#define EFLASH_CTRL1_CKDIV_LOCK_Pos       (8UL)                     /*!< CKDIV_LOCK (Bit 8)                                    */
#define EFLASH_CTRL1_CKDIV_LOCK_Msk       (0x100UL)                 /*!< CKDIV_LOCK (Bitfield-Mask: 0x01)                      */
#define EFLASH_CTRL1_SPEED_LATENCY_Pos    (12UL)                    /*!< SPEED_LATENCY (Bit 12)                                */
#define EFLASH_CTRL1_SPEED_LATENCY_Msk    (0x3000UL)                /*!< SPEED_LATENCY (Bitfield-Mask: 0x03)                   */
/* =======================================================  WPRT_EN0  ======================================================== */
#define EFLASH_WPRT_EN0_WPRT_EN0_Pos      (0UL)                     /*!< WPRT_EN0 (Bit 0)                                      */
#define EFLASH_WPRT_EN0_WPRT_EN0_Msk      (0xffffffffUL)            /*!< WPRT_EN0 (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  WPRT_EN1  ======================================================== */
#define EFLASH_WPRT_EN1_WPRT_EN1_Pos      (0UL)                     /*!< WPRT_EN1 (Bit 0)                                      */
#define EFLASH_WPRT_EN1_WPRT_EN1_Msk      (0xffffffffUL)            /*!< WPRT_EN1 (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  CTRL2  ========================================================= */
#define EFLASH_CTRL2_PVDMON_EN_Pos        (28UL)                    /*!< PVDMON_EN (Bit 28)                                    */
#define EFLASH_CTRL2_PVDMON_EN_Msk        (0x10000000UL)            /*!< PVDMON_EN (Bitfield-Mask: 0x01)                       */
#define EFLASH_CTRL2_PVD_WRN_Pos          (31UL)                    /*!< PVD_WRN (Bit 31)                                      */
#define EFLASH_CTRL2_PVD_WRN_Msk          (0x80000000UL)            /*!< PVD_WRN (Bitfield-Mask: 0x01)                         */

/** @} */ /* End of group PosMask_peripherals */


#ifdef __cplusplus
}
#endif

#endif /* AC780X_H */


/** @} */ /* End of group AC780X */

/** @} */ /* End of group AutoChips */
